US008831160B2 (12) United States Patent (10) Patent No.: US 8,831,160 B2 Ferris et al. (45) Date of Patent: Sep. 9, 2014 (54) METHOD AND APPARATUS FOR USPC ........... 375/362; 375/215; 375/295; 375/309; SWITCHING CLOCK FREQUENCY INA 375/354; 375/377 SYSTEM-N-PACKAGE DEVICE (58) Field of Classification Search CPC ....... H04L 7/00, H04L 770004: H04L 7/0008; (71) Applicants: STMicroelectronics (Research & HO4L 7/0083: HO4N 19/00478: HO4N Development) Limited, Marlow (GB); 19/00484; H04N 19/00781; H04N 19/00951; STMicroelectronics (Grenoble 2) SAS, HO4N 19/00121: HO4N 19/00533; HO4N Grenoble (FR) 19/00775, H04N 19/00884; H04B 7/18532: HO3K 1.9/OO13 (72) Inventors: Andrew Ferris, Bristol (GB), Ignazio USPC ......... 375/215, 286, 295,306, 309, 326,339, Antonino Urzi, Voreppe (FR) 375/354, 362. 377 (73) Assignees: STMicroelectronics (Research & See application file for complete search history. Development) Limited, Marlow, 56 Ref Cited Buckinghamshire (GB); (56) eeees e STMicroelectronics (Grenoble 2) SAS, U.S. PATENT DOCUMENTS Grenoble (FR) 3,594,656 A 7, 1971 Tsukamoto (*) Notice: Subject to any disclaimer, the term of this 5,357,146 A * 10/1994 Heimann ...................... 327,292 patent is extended or adjusted under 35 (Continued) U.S.C. 154(b) by 31 days. FOREIGN PATENT DOCUMENTS (21) Appl. No.: 13/744,146 JP 2003.13.1754. A 5, 2003 (22) Filed: Jan. 17, 2013 WO WO-9906543 A1 2, 1999 OTHER PUBLICATIONS (65) Prior Publication Data US 2013/O195235A1 Aug. 1, 2013 UKIPO Search Report for GB120 1530.1 mailed May 16, 2012, with Corrected Citation Pages (6 pages). (30) Foreign Application Priority Data Primary Examiner—Hirdepal Singh Jan. 30, 2012 (GB) ................................... 1201530.1 (74) Attorney, Agent, or Firm — Gardere Wynne Sewell LLP (51) Int. Cl. (57) ABSTRACT H04L 7/04 (2006.01) An apparatus includes a first clock Source, a second clock G06F L/10 (2006.01) Source and circuitry configured to Supply a clock signal to a G06F L/08 (2006.01) circuit. The circuitry operates to change the clock signal from HO4L 7/OO (2006.01) one frequency to another different frequency. This change is (52) U.S. Cl. made in a manner whereby no clock signal is Supplied during CPC. H04L 7/00 (2013.01); G06F I/10 (2013.01); a period of time when the change from the one frequency to H04L 7/0083 (2013.01); H04L 7/0004 the another different clock frequency is being made. (2013.01); G06F I/08 (2013.01); H04L 70008 (2013.01) 27 Claims, 13 Drawing Sheets 22 16 30 2 EN ot 13 l fg 2 | ATA is ckx 8 Y C K CONTROL GEN ciklose i PHY 28a US 8,831,160 B2 Page 2 (56) References Cited 8,375,239 B2 * 2/2013 Nara et al. .................... T13/400 2004/0012435 A1* 1/2004 Meguro ....... ... 327,408 U.S. PATENT DOCUMENTS 2007,0291,828 A1* 12/2007 Martin et al. ... 375,219 2008/0307240 A1* 12/2008 Dahan et al. .................. T13,320 6,088,255 A 7/2000 Matsuzaki et al. 2009, O154268 A1 6/2009 Kinugasa et al. 6,201.448 B1 3, 2001 Tam et al. 2011/O140789 A1* 6, 2011 Kumar ............................ 331, 18 6,452.426 B1* 9/2002 Tamarapalliet al. ........... 327/99 2011/0225341 A1* 9, 2011 Satoh et al. ................... T10,314 6,483,888 B1 * 1 1/2002 Boerstler et al. ................ 377/47 2012/0306558 A1* 12/2012 Singvallet al. 327,298 7.467,320 B2 * 12/2008 Chang et al. ....... 713,501 2013,0083611 A1* 4, 2013 Ware et al. ... 365,191 7,656,980 B2 * 2/2010 Matsumuro et al. 375,354 2013/01291 14 A1* 5, 2013 Lesso .............................. 381.98 7,729,415 B1* 6/2010 Possley .......... 375,219 8,217,697 B2 * 7/2012 Satterfield ..................... 327,291 * cited by examiner U.S. Patent Sep. 9, 2014 Sheet 1 of 13 US 8,831,160 B2 O NOX C NiOOX. OSNOX. ONOOX U.S. Patent Sep. 9, 2014 Sheet 2 of 13 US 8,831,160 B2 U.S. Patent Sep. 9, 2014 Sheet 3 of 13 US 8,831,160 B2 $3$1Kild U.S. Patent US 8,831,160 B2 {{}}. U.S. Patent Sep. 9, 2014 Sheet 5 of 13 US 8,831,160 B2 f ce S. S U.S. Patent Sep. 9, 2014 Sheet 6 of 13 US 8,831,160 B2 S s g w C U.S. Patent Sep. 9, 2014 Sheet 7 of 13 US 8,831,160 B2 *---, S N U.S. Patent Sep. 9, 2014 Sheet 8 of 13 US 8,831,160 B2 ser U.S. Patent Sep. 9, 2014 Sheet 9 of 13 US 8,831,160 B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - U.S. Patent Sep. 9, 2014 Sheet 10 of 13 US 8,831,160 B2 Z|| ±C) & AAS ar c U.S. Patent US 8,831,160 B2 U.S. Patent Sep. 9, 2014 Sheet 12 of 13 US 8,831,160 B2 QSO|(1008) U.S. Patent Sep. 9, 2014 Sheet 13 of 13 US 8,831,160 B2 a - - - - - - - - - - - as a as - - - - - - - - - - - as a US 8,831,160 B2 1. 2 METHOD AND APPARATUS FOR BRIEF DESCRIPTION OF THE DRAWINGS SWITCHING CLOCK FREQUENCY INA SYSTEM-N-PACKAGE DEVICE For an understanding of some embodiments, reference is made by way of example only to the accompanying Figures in PRIORITY CLAIM which: FIG. 1 shows a first die and a second die; The present application claims priority from Great Britain FIG. 2 shows the part of the transmitter physical interface Application for Patent No. 1201530.1 filed Jan. 30, 2012, the and associated circuitry in more detail; disclosure of which is incorporated by reference. FIG.3 shows in more detail the transmitter physical inter 10 face of FIGS. 1 and 2: TECHNICAL FIELD FIG. 4 shows the transmitter physical interface control circuitry of the arrangement of FIG. 1; The present invention relates to a method and an arrange FIG.5 shows in detail the delay chains of the control circuit ment and in particular but not exclusively to a method and 15 of FIG. 4; arrangement for use when a clock frequency is changed. FIG. 6 shows in detail the DLL control circuitry; FIG. 7 shows a timing diagram; BACKGROUND FIG. 8 shows a detailed timing diagram during the fre quency Switching phase; In known circuits, a clock frequency is sometimes changed FIG. 9 shows a detailed timing diagram of the reverse from one value to another. This can cause problems of, for frequency switch to that of FIG. 8: example, clock glitches and skewing. This may be problem FIG. 10 shows a transmitter physical interface control cir atic when data is being clocked using the changing clock. cuitry of a second embodiment; SUMMARY FIG. 11 shows a counter circuit of the transmitter physical 25 interface control circuitry of FIG. 10; FIG. 12 shows a timing diagram for the second embodi In an embodiment, an apparatus comprises: a first clock ment; and Source: a second clock source; and circuitry configured to FIG. 13 shows a detailed timing diagram during the fre Supply a clock signal to a circuit, said circuitry configured to quency Switching phase. change the clock signal from one frequency to another differ 30 ent frequency Such that no clock signal is Supplied when DETAILED DESCRIPTION OF THE DRAWINGS changing from said one frequency to a said another different clock frequency. Some embodiments may be used where there are more than In an embodiment, an apparatus comprises: a transmit one die within a single package. In particular, a plurality of physical interface including a data output and a clock output 35 integrated circuit dies may be incorporated within a single which is a timing reference for the data output; a first oscil package. In the following examples, FIG. 1 shows a single lating circuit configured to generate a first clock signal having System-in-Package having two dies which is provided to a variable frequency; and a second oscillating circuit config explain in detail the interaction between two dies. However it ured to generate a second clock signal at a fixed frequency. A is appreciated that three or more dies may be provided in control circuit is configured to control operation of the trans 40 Some embodiments in the same single package. mit physical interface during a change in frequency of the The rationale for the increasingly common usage of two, or clock output, said control circuit operable to: terminate trans more, separate die in a single System-in-Package (SiP) fol mit physical interface data output with the clock output lows: derived from the first clock signal; activate transmit physical The decreasing feature size in CMOS silicon processes interface data output with the clock output derived from the 45 allows digital logic to shrink significantly in Successive fab second clock signal; change frequency of the first clock sig rication technology. For example, an area shrink of approxi nal; terminate transmit physical interface data output with the mately 50% may be obtained when comparing a digital logic clock output derived from the second clock signal; and acti cell implemented in 90 nanometer technology with a digital vate transmit physical interface data output with the clock logic cell implemented in 65 nanometer technology. How output derived from the first clock signal at the changed 50 ever, analog and input/output cells tend to shrink much less if frequency. at all in these implementations. This may lead to increasingly In an embodiment, a method comprises: transmitting data pad limited designs in many complex system-on-chips (SoC).