Verilog VHDL vs. Verilog: Process Block • Verilog is an alternative language to VHDL for Process Block specifying RTL for logic synthesis VHDL: • VHDL similar to Ada programming language in process (siga, sigb) Both used to specify blocks begin syntax of logic with multiple …... inputs/outputs • Verilog similar to C/Pascal programming language end; Verilog: • VHDL more popular with European companies, always @ (siga or sigb) Verilog more popular with US companies. begin …. • VHDL more ‘verbose’ than Verilog. end • Verilog and VHDL do RTL modeling equally well. BR 1/00 1 BR 1/00 2 VHDL vs. Verilog: Signal Assignment VHDL vs. Verilog: Interface Declaration VHDL: VHDL: entity mux is VERILOG: signal a, b, c, d: std_logic; port ( a,b, s: in std_logic; module mux (a,b,s,y); begin y : out std_logic); input a,b,s; output y; a <= b and c; architecture a of mux is d < = (c or b) xor (not (a) and b); begin …. end; …… endmodule Declarations for end; VERILOG: one-bit wires are wire a,b,c,d; optional. assign a = b & c; Logical operators assign d = (c | b) ^ (~a & b); same as in C. BR 1/00 3 BR 1/00 4 A Sample Model (RTL), assignment statement VHDL vs. Verilog: Busses Description VHDL: Implementation signal a,c: std_logic_vector(7 downto 0); begin a(3 downto 0) <= c (7 downto 4); module majconc (a,b,c,y); c(0) <= ‘0’; input a,b,c; c<= “00001010”; output y; end; Verilog: wire [7:0] ; assign y = (a & b) | (a & c) | (b &c) ; begin assign a[3:0] = b[7:4]; endmodule assign a[0] <= 0; assign a = ‘b0000000; end; Value specified in binary. BR 1/00 5 BR 1/00 6 1 A Sample Model (RTL), ‘always’ block A Sample Model ( Gate Level Primitives, built into language) Description Description Implementation Implementation module majconc (a,b,c,y); module majconc (a,b,c,y); input a,b,c; input a,b,c; output y; output y; Gate primitive reg y; name Must use ‘reg’ declaration if and I0 (n1, a, b); VHDL does not always @(a or b or c) Instance name begin signal assigned from always and I1 (n2, a, c); have the y = (a & b) | (a & c) | (b &c) ; block. and I2 (n3, b, c); or I3 (y, n1, n2, n3); Output equivalent of end gate-level Process triggered on any endmodule primitives endmodule Non blocking change on signals a,b,c . Inputs assignment BR 1/00 7 BR 1/00 8 Asynchronous vs Synchronous Inputs nonblocking vs blocking assignments reg q; Synchronous reset, • A nonblocking assignment (<=) samples right hand always @(posedge clk) begin high true side (RHS) at beginning of timestep; with the actual if (r) q <= 0; else q <= d; assignment (the LHS) taking place at the end of the timestep – Works like a signal assignment in VHDL reg q; Asynchronous reset –, always @(posedge clk or posedge r) high true. • A blocking assignment (=) will evaluate the RHS begin and perform the LHS assignment without Need ‘posedge’ on ‘r’ if ( r) then q <= 0; interruption from another Verilog statement else q <= d; because Verilog syntax end Non- requires if any signals – Works like a variable assignment (:=) in VHDL blocking are edge-triggered in • Should use nonblocking assignments in always assignment Style suggested by C. Cummings, SNUG 2002 event list, all signals blocks used to synthesize/simulate sequential logic. must be edge- BR 1/00triggered. 9 BR 1/00 10 Nonblocking Assignments More on nonblocking assignments module timetest (y1,y2,a,clk); module timetest (y1,y2,a,clk); output y1,y2; output y1,y2; input a,clk; input a,clk; reg y1,y2; reg y1,y2; always @(posedge clk) begin With nonblocking always @(posedge clk) begin y1 <= a; assignments, ordering of end y1 <= a; these always blocks y2 <= y1; Synthesis results in DFF end always @(posedge clk) begin does not affect RTL chain endmodule y2 <= y1; simulation or ay1y2 end synthesized gates. D Q D Q endmodule Nonblocking assignment C C BR 1/00 11 BR 1/00 12 2 When to use blocking assignments Some Rules Use blocking assignments for always blocks that are purely • The paper by Cummings lists several rules for combinational writing Verilog in which RTL simulation will reg y, t1, t2; match synthesized gate level simulation. The always @(a or b or c or d) begin t1 = a & b; most important of these rules are: t2 = c & d; RTL simulation and – Use blocking assignments in always blocks that are y = t1 | t2; synthesis results match purely combinational end – Use only nonblocking assignments in always blocks that are either purely sequential or have a mixture of combinational and sequential assignments. • If you understand the differences between blocking and nonblocking assignments in terms of simulation, then these rules are self-evident. BR 1/00 13 BR 1/00 14 Verilog Vs. VHDL • Verilog and VHDL are equivalent for RTL modeling (code that will be synthesized). • For high level behavioral modeling, VHDL is better – Verilog does not have ability to define new data types – Other missing features for high level modeling • Verilog has built-in gate level and transistor level primitives – Verilog much better than VHDL at below the RTL level. • Bottom Line: You should know both!!!!! BR 1/00 15 3.