Harris Real Time Express™ Background information on a new concept for real time control, plus descriptions of the RTX™ software development system, development board, toolbox, and the FORTH environment. {II HARR.IS, Real Time Express™, and RTX ™ are trademarks of Harris Corporation HARRIS SEMICONDUCTOR © 1988 Table of Contents PAGE Harris RTX: a new concept for real time control What are the requirements for "real time" ...................................................... High speed microcontrollers - a new alternative . 1 RTX 2000- performance through simplicity/parallelism . 2 Substituting parallelism for pipelining . 2 Stack based processors .................................................................... : 3 RTX - providing flexible hardware/software partitioning . 3 RTX vs. conventional RISC processors......................................................... 3 RTX multi-tasking . ... .. .. 4 FORTH: well suited for real time systems . 4 RTX compilers for other languages ............................ , . 5 RTX 2000 - well suited for real time Al . 5 RTX algorithmic coprocessors................................................................ 5 Real time software development complexity . 6 Structured programming support . 6 High level language operation . 6 Software productivity. 7 Real time debug . 7 Rapid time to market . 7 RTX questions and answers . 8 Software development system . 12. Development board . .14 . Toolbox ...................................................................................... 16 FORTH: a software development environment . 23. Harris Semiconductor sales headquarters ........................................................ 24 Real Time Express, RTX, RTX 2000, RTXDS, RTXDB, RTX Toolbox, Harris RTX, and ASIC Bus are Trademarks of Harris Corporation Harris Real Time Express A New Concept For Real-Time Control WHAT ARE THE REQUIREMENTS FOR "REAL TIME?" HIGH SPEED MICROCONTROLLERS - A NEW ALTERNATIVE TO CONVENTIONAL MICRO­ "How fast is fast enough for real time?" is a complicated PROCESSORS FOR REAL TIME question because of the application specific nature of real time computing. For example, an acceptable real time Most conventional microprocessors are optimized for an response for a transaction processing system· might be a office automation computer or computer-aided workstation half-second response to a query. For an avionic control compJting environment. Significant complexity is added to system, however, a half-second response to an external these tnachines in order to support th~ memory manage­ event is likely to be too slow. For the former, conventional ment and general purpose data processing requirements of data processing type processors are clearly an effective these applications. Microcontrollers, on the other hand, take solution to real time requirements, but in many applications advantage of the increased circuit density made possible by -- data acquisition, process control, robotics, local area advances in silicon processing to enhance the device for network controllers, digital sigf')al processing -- the controller or othe,r specific applications. This has produced response within a critical time period is extremely important. a large variety of devices that are useful for specific applica­ As a result, real time can only be defined within the context tions as well as microcontrollers for more general purpose of the end application. It is driven by the processing require­ use. However, microcontrollers have traditionally been ments to meet time critical external events. much slower than microprocessors and have not been optimized to support real time applications. Many computers need fast instruction execution speeds. However, for real time applications interrupt latency and context switch times are important specifications in addition Microcontrollers can be broadly classified as either applica­ to the raw instruction execution speed of a processor. tion generic or application specific. The generic products, Recent advances in hardware and software have reduced such as the RTX 2000, provide solutions for a broad variety response times for interrupts and context switches down an of applications. The RTX 2000, however, with its unique order of magnitude for many processors, to the many tens ASIC Bus, provides the capability of optimizing the solution of microseconds or many hundreds of microseconds, by simplifying the partitioning between hardware and soft­ respectively. The RTX 2000 brings these response times ware through the use of external ASIC peripherals. The down another order magnitude to 400 nanoseconds for obvious extension to this philosophy is to incorporate those interrupt response time,and two microseconds for context peripherals on the ASIC Bus within the IC. Therefore, appli­ switch time, while achieving an instruction execution rate cation specific devices (both standard product or customer over 1O MIPS. specific) can be developed as a natural extension to the core processor. A key consideration for real-time processing is predictability. Most general purpose computers have features to improve average instruction execution times. The emergence of high speed 16-bit microcontrollers provi­ Features such as pipelines, caches, on-chip registers, and des a new opportunity to replace hardware with software. A optimizing compilers all contribute to an improvement in major limitation to the ability to replace hardware with soft­ average execution rate. But, they also contribute to more ware has been the performance constraints of software uncertainty with respect to critical timing predictability. As a solutions. Th~ RTX 2000's substantial increase in result, external logic, such as OMA controllers or 1/0 performance provides new opportunities to replace random processors, must be provided to support all but the most logic with software providing significant improvements in routine interface requirements with the externJ1 world. The flexibility and time to market. For example, because of the RTX 2000 significantly contributeS, to moving more very high speed of the RTX 2000, a full duplex UART can be hardware into software as a result 'of high instruction emulated in software and requires less than 1 o/o of the pro­ execution rate, rapid responses to external events and pre­ cessor's bandwidth to perform the functionality of a 1500 dictable timing of instruction execution. gate UART. RTX 2000 - PERFORMANCE THROUGH SIMPLICITY/ completely different. Furthermore, conventional machines PARALLELISM do not support efficient subroutine calls. Many clock cycles are required for managing the internal operations. The RTX 2000 achieves performance through simplicity. The chip is designed for simplicity. It has no pipeline; no The RTX 2000 uses simple, and fast hardware to execute microcode sequencer; and no microcode. All instructions high semantic content instructions that closely reflect the except memory access instructions execute in one cycle structure of the program. Performance is not penalized for (memory access instructions execute in two). The RTX organizing programs into small, compact, understandable 2000 minimizes address calculation delays by incorpora­ procedures. This results in compact program structures that ting a simplified memory paging mechanism, and eliminates are composed of hierarchically arranged solutions to sub­ the complexity of multiple addressing modes and memory problems. Thus programs can be simultaneously optimized management. The RTX 2000 is a stack machine. Stacks fa­ for small memory space, fast execution speed, and low cilitate the evaluation of expressions and minimize the con­ development costs. This allows the hardware/software trol overhead needed to organize data. The stack uses only environment to deliver cost effective solutions to the users a single pointer register to keep track of and access its data. problems. A stack machine not only uses a stack for temporary data storage, but executes all operations on data from the stack. SUBSTITUTING PARALLELISM FOR PIPELINING The ALU thus finds all of its data in a pre-defined location, IMPROVES SPEED WHILE IMPROVING REAL TIME and can get that data without an address specification. In RESPONSIVENESS addition, no addresses need to be compiled for stack access. The RTX 2000 also has a hardware return stack Pipelining is a common architectural strategy to increase which handles subroutine return addresses. This stack can the speed for conventional processors. For example, also be used for temporary data storage as well. portions of a processor concentrate on fetching instructions, fetching operands, computing values, compu­ The RTX 2000 instruction set is sub-divided into six ting next addresses, and storing results. This method is a instruction classes, with each section controlling a hard­ very efficient mechanism to increase speed for sequentially ware operation. Like horizontally micro coded bit slice executing programs at a relatively small cost of added hard­ architecture instructions, multiple operations can be ware complexity. However, pipelining impacts the timing of compacted and coded within a single OP code to execute instruction response to subroutine calls, interrupts, and in parallel. Four separate buses for the data stack, return context switching, and the speed increases achieved by stack, memory and ASIC Bus and operate in parallel, signifi­ pipelining can be lost for highly structured programs. cantly increasing instruction execution efficiency. For example, the OP code BE68