Vivado Design Suite User Guide Logic Simulation UG900 (v2014.1) April 23, 2014 Revision History The following table shows the revision history for this document. Date Version Revision 04/23/2014 2014.1 Coded example for running a post-synthesis functional simulation from the command line corrected, page 112. Corrected information about switches in the section Compiling Simulation Libraries for VCS, page 149. Updated usage information on VCS Script Simulation, page 152. Added Appendix D, SystemVerilog Constructs Supported by the Vivado Simulator (early access). IDS_lite is obsolete; references to it have been removed. General updates made to reflect changes in version 2014.1, including SystemVerilog information, updates to graphics. Revisions and enhancements throughout, including updates to cross references and citations; addition of instructions on locating and displaying GUI features. Logic Simulation www.xilinx.com Send Feedback 2 UG900 (v2014.1) April 23, 2014 Table of Contents Chapter 1: Logic Simulation Overview Introduction . 6 Simulation Flow . 6 Supported Simulators . 9 Language and Encryption Support . 10 OS Support and Release Changes . 10 Chapter 2: Understanding Simulation Components in Vivado Introduction . 11 Using Test Benches and Stimulus Files . 12 Using Xilinx Simulation Libraries. 13 Compiling Simulation Libraries . 24 Understanding the Simulator Language Option . 25 Using the export_simulation Command. 27 Recommended Simulation Resolution . 29 Generating a Netlist. 29 Annotating the SDF File . 30 Using Global Reset and 3-State. 31 Delta Cycles and Race Conditions . 33 Using the ASYNC_REG Constraint . 34 Simulating Configuration Interfaces. 35 Disabling Block RAM Collision Checks for Simulation . 39 Dumping the Switching Activity Interchange Format File for Power Analysis . 40 Chapter 3: Using the Vivado Simulator from the Vivado IDE Introduction . 41 Vivado Simulator Features . 41 Adding or Creating Simulation Source Files . 42 Running the Vivado Simulator . 51 Running Post-Synthesis Simulation . 59 Running Post-Implementation Simulations . 61 Identifying Between Multiple Simulation Runs. 62 Pausing a Simulation . 62 Logic Simulation www.xilinx.com Send Feedback 3 UG900 (v2014.1) April 23, 2014 Saving Simulation Results . 63 Closing Simulation . 63 Adding a post.tcl Batch File. 63 Skipping Compilation or Simulation . 64 Viewing Simulation Messages. 64 Chapter 4: Analyzing with the Vivado Simulator Waveforms Introduction . 66 Using Wave Configurations and Windows. 66 Opening a Previously Saved Simulation Run . 68 Understanding HDL Objects in Waveform Configurations . 69 Customizing the Waveform. 74 Controlling the Waveform Display . 82 Organizing Waveforms . 84 Analyzing Waveforms . 86 Using Force Options. 89 Chapter 5: Using Vivado Simulator Command Line and Tcl Introduction . 93 Compiling and Simulating a Design . 93 Elaborating and Generating a Design Snapshot. 95 Simulating the Design Snapshot . 100 Example of Running Vivado Simulator in Standalone Mode . 107 Project File (.prj) Syntax . 108 Predefined Macros. 109 Library Mapping File (xsim.ini) . 109 Running Simulation Modes . 111 Using Tcl Commands and Scripts . 113 Tcl Property Commands . 114 Chapter 6: Debugging a Design with Vivado Simulator Introduction . 118 Debugging at the Source Level . 118 Generating (forcing) Stimulus . 121 Power Analysis Using Vivado Simulator. 126 Using the report_drivers Tcl Command . 127 Using the Value Change Dump Feature . 128 Chapter 7: Simulating with QuestaSim/ModelSim Introduction . ..