SILICON ON FERROELECTRIC INSULATOR FIELD EFFECT TRANSISTOR (SOFFET): A RADICAL ALTERNATIVE TO OVERCOME THE THERMIONIC LIMIT A DISSERTATION IN Electrical and Computer Engineering & Physics Presented to the Faculty of the University of Missouri – Kansas City in partial fulfillment of the Requirements for the degree DOCTOR OF PHILOSOPHY By Azzedin D. Es-Sakhi Master of Science (MS) in Electrical and Computer Engineering, University of Missouri- Kansas City, USA 2013 Kansas City, Missouri 2016 ©2016 Azzedin D. Es-Sakhi ALL RIGHTS RESERVED SILICON ON FERROELECTRIC INSULATOR FIELD EFFECT TRANSISTOR (SOFFET): A RADICAL ALTERNATIVE TO OVERCOME THE THERMIONIC LIMIT Azzedin D. Es-Sakhi, Candidate for the Doctor of Philosophy Degree University of Missouri - Kansas City, 2016 ABSTRACT The path of down-scaling traditional MOSFET is reaching its technological, economic and, most importantly, fundamental physical limits. Before the dead-end of the roadmap, it is imperative to conduct a broad research to find alternative materials and new architectures to the current technology for the MOSFET devices. Beyond silicon electronic materials like group III-V heterostructure, ferroelectric material, carbon nanotubes (CNTs), and other nanowire-based designs are in development to become the core technology for non-classical CMOS structures. Field effect transistors (FETs) in general have made unprecedented progress in the last few decades by down-scaling device dimensions and power supply level leading to extremely high numbers of devices in a single chip. High- density integrated circuits are now facing major challenges related to power management and heat dissipation due to excessive leakage, mainly due to subthreshold conduction. Over the years, planar MOSFET dimensional reduction was the only process followed by the semiconductor industry to improve device performance and to reduce the iii power supply. Further scaling increases short-channel-effect (SCE), and off-state current makes it difficult for the industry to follow the well-known Moore’s Law with bulk devices. Therefore, scaling planar MOSFET is no longer considered as a feasible solution to extend this law. The down-scaling of metal-oxide-semiconductor field effect transistors (MOSFETs) leads to severe short-channel-effects and power leakage at large-scale integrated circuits (LSIs). The device, which is governed by the thermionic emission of the carriers injected from the source to the channel region, has set a limitation of the subthreshold swing (S) of 60 푚푉/푑푒푐푎푑푒 at room temperature. Devices with ‘S’ below this limit is highly desirable to reduce the power consumption and maintaining a high 퐼표푛/퐼표푓푓 current ratio. Therefore, the future of semiconductor industry hangs on new architectures, new materials or even new physics to govern the flow of carriers in new switches. As the subthreshold swing is increasing at every technology node, new structures using SOI, multi-gate, nanowire approach, and new channel materials such as III–V semiconductor have not satisfied the targeted values of subthreshold swing. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic- emission limit of 60 푚푉/푑푒푐푎푑푒. This value was unbreakable by the new structure (SOI- FinFET). On the other hand, most of the preview proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for sub-60 mV/decade designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This dissertation also proposes a novel iv design that exploits the concept of negative capacitance. The new field-effect-transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field- effect-transistor (SOFFET). This proposal is a promising methodology for future ultra- low-power applications because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers a subthreshold swing significantly lower than 60 푚푉/푑푒푐푎푑푒 and reduced threshold voltage to form a conducting channel. The proposed SOFFET design, which utilizes the negative capacitance of a ferroelectric insulator in the body-stack, is completely different from the FeFET and NCFET designs. In addition to having the NC effect, the proposed device will have all the advantages of an SOI device. Body-stack that we are intending in this research has many advantages over the gate-stack. First, it is more compatible with the existing processes. Second, the gate and the working area of the proposed SOFFET is like the planar MOSFET. Third, the complexity and ferroelectric material interferences are shifted to the body of the device from the gate and the working area. The proposed structure offers better scalability and superior constructability because of the high-dielectric buried insulator. Here we are providing a very simplified model for the structure. Silicon-on-ferroelectric leads to several advantages including low off-state current and shift in the threshold voltage with the decrease of the ferroelectric material thickness. Moreover, having an insulator in the body of the device increases the controllability over the channel, which leads to the reduction in the short-channel-effect (SCE). The proposed SOFFET offers low value of subthreshold swing (S) leading to better performance in the on-state. The off-state current is directly related to S. So, the off-state current is also minimum in the proposed structure. v APPROVAL PAGE The faculty listed below, appointed by the Dean of the School of Graduate Studies, have examined a dissertation titled “Silicon-on-Ferroelectric Insulator Field Effect Transistor (SOFFET): A Radical Alternative to Overcome the Thermionic Limit” presented by Azzedin Es-Sakhi, candidate for the Doctor of Philosophy degree, and hereby certify that in their opinion it is worthy of acceptance. Supervisory Committee Masud H Chowdhury Ph.D., Committee Chair Associate Professor, Department of Computer Science & Electrical Engineering Ghulam M. Chaudhry, Ph.D. Professor and Computer Science & Electrical Engineering Department Chair Praveen Rao, Ph.D. Associate Professor, Department of Computer Science & Electrical Engineering Deb Chatterjee, Ph.D. Associate Professor, Department of Computer Science & Electrical Engineering Anthony Caruso, Ph.D. Professor, Department of Physics & Astronomy vi CONTENTS ABSTRACT ....................................................................................................................... iii LIST OF ILLUSTRATIONS ............................................................................................ xii ACKNOWLEDGEMENTS ............................................................................................. xvi LIST OF ACRONYMS .................................................................................................. xvii LIST OF SYMBOLS ....................................................................................................... xix Chapter 1 INTRODUCTION .................................................................................................... 1 1.1. Organization ...................................................................................................... 1 1.2. Thesis Objectives .............................................................................................. 2 1.3. Nanotechnology Challenges .............................................................................. 3 1.4. Recent and Emerging Device Technologies ..................................................... 4 1.4.1. Emerging field of ultra low-power devices .......................................... 4 1.4.2. Silicon-on-insulator (SOI) devices ..................................................... 11 1.4.3. Carbon nanotube field-effect-transistor (CNTFET) ........................... 12 1.4.4. Multi-gate transistors.......................................................................... 13 1.4.5. Tunneling field effect transistors (TFETs) ......................................... 14 1.4.6. Negative capacitance gate-stack transistors ....................................... 16 1.5. Contribution .................................................................................................... 17 2 SUBTHRESHOLD SWING .................................................................................... 18 vii Introduction ...................................................................................................... 18 Subthreshold Region ........................................................................................ 19 How to Achieve S Less than 60mV/decade ..................................................... 23 High-κ Gate Insulator ....................................................................................... 25 3 MULTI-GATE DEVICES ....................................................................................... 27 3.1 SOI and Multi-gate Devices ............................................................................. 27 3.2 Silicon-On-Insulator Transistors (SOI) ............................................................ 28 3.3 The Road to Multi-gate Devices ...................................................................... 29 3.4 Introducing the FinFET ...................................................................................