Geode™ GXm Processor Integrated x86 Solution with MMX Support April 2000 Geode™ GXm Processor Integrated x86 Solution with MMX Support General Description The National Semiconductor® Geode™ GXm processor graphics accelerator provides pixel processing and ren- is an advanced 32-bit x86 compatible processor offering dering functions. high performance, fully accelerated 2D graphics, a 64-bit A separate on-chip video buffer enables >30 fps MPEG1 synchronous DRAM controller and a PCI bus controller, video playback when used together with the CS5530 I/O all on a single chip that is compatible with Intel’s MMX companion chip. Graphics and system memory accesses technology. are supported by a tightly-coupled synchronous DRAM The GXm processor core is a proven design that offers (SDRAM) memory controller. This tightly coupled memory competitive CPU performance. It has integer and floating subsystem eliminates the need for an external L2 cache. point execution units that are based on sixth-generation The GXm processor includes Virtual System Architec- technology. The integer core contains a single, six-stage ture® (VSA™ technology) enabling XpressGRAPHICS execution pipeline and offers advanced features such as and XpressAUDIO subsystems as well as generic emula- operand forwarding, branch target buffers, and extensive tion capabilities. Software handler routines for the Xpress- write buffering. A 16 KB write-back L1 cache is accessed GRAPHICS and XpressAUDIO subsystems can be in a unique fashion that eliminates pipeline stalls to fetch included in the BIOS and provide compatible VGA and 16- operands that hit in the cache. bit industry standard audio emulation. XpressAUDIO tech- In addition to the advanced CPU features, the GXm pro- nology eliminates much of the hardware traditionally asso- cessor integrates a host of functions which are typically ciated with audio functions. implemented with external components. A full-function Geode™ GXm Processor Internal Block Diagram Write-Back Integer MMU FPU Cache Unit Unit C-Bus Internal Bus Interface Unit X-Bus Integrated Graphics Memory Display PCI Functions Pipeline Controller Controller Controller SDRAM Port CS5530 PCI Bus (CRT/LCD TFT) National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode and VSA are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks. © 2000 National Semiconductor Corporation www.national.com Features General Features 2D Graphics Accelerator Packaged in: Graphics pipeline performance significantly increased — 352-Terminal Ball Grid Array (BGA) or over previous generations by pipelining burst — 320-Pin Staggered Pin Grid Array (SPGA) reads/writes 0.35-micron four layer metal CMOS process Accelerates BitBLTs, line draw, text Split rail design (3.3V I/O and 2.9V core) Supports all 256 raster operations Supports transparent BLTs Geode™ GXm Processor 32-Bit x86 Processor Runs at core clock frequency Supports the MMX instruction set extension for the acceleration of multimedia applications Full VGA and VESA mode support Speeds offered up to 266 MHz Special "Driver level” instructions utilize internal scratchpad for enhanced performance 16 KB unified L1 cache Integrated Floating Point Unit (FPU) Display Controller Re-entrant System Management Mode (SMM) Video Generator (VG) improves memory efficiency for enhanced for VSA display refresh with SDRAM Supports a separate MPEG1 video buffer and data PCI Controller path to enable video acceleration in the CS5530 Fixed, rotating, hybrid, or ping-pong arbitration Internal palette RAM for use with the CS5530 Supports up to three PCI bus masters Direct interface to CS5530 for CRT and TFT flat panel Synchronous CPU and PCI bus clock frequency support which eliminates need for external RAMDAC Supports concurrency between PCI master and L1 Hardware frame buffer compressor/decompressor cache Hardware cursor Power Management Supports up to 1280x1024x8 bpp and 1024x768x16 bpp Designed to support CS5530 power management architecture XpressRAM Subsystem CPU only Suspend or full 3V Suspend supported: Memory control/interface directly from CPU — Clocks to CPU core stopped for CPU Suspend — All on-chip clocks stopped for 3V Suspend 64-Bit wide memory bus — Suspend refresh supported for 3V Suspend Support for: — Two 168-pin unbuffered DIMMs Virtual Systems Architecture Technology — Up to 16 open banks simultaneously Architecture allows OS independent (software) virtual- — Single or 16-byte reads (burst length of two) ization of hardware functions Provides compatible high performance legacy VGA core functionality Note: GUI (Graphical User Interface) graphics accel- eration is pure hardware. Provides 16-bit XpressAUDIO subsystem www.national.com 2 Revision 3.1 Geode™ GXm Processor Table of Contents 1.0 ArchitectureOverview............................................. 8 1.1 INTEGERUNIT ...........................................................8 1.2 FLOATINGPOINTUNIT ....................................................9 1.3 WRITE-BACKCACHEUNIT .................................................9 1.4 MEMORYMANAGEMENTUNIT..............................................9 1.4.1 InternalBusInterfaceUnit............................................9 1.5 INTEGRATED FUNCTIONS . .............................................9 1.5.1 Graphics Accelerator . .............................................9 1.5.2 DisplayController..................................................10 1.5.3 XpressRAMMemorySubsystem......................................10 1.5.4 PCIController.....................................................10 1.6 GEODEGXM/CS5530SYSTEMDESIGNS ....................................11 2.0 SignalDefinitions................................................ 13 2.1 PINASSIGNMENTS ......................................................13 2.2 SIGNALDESCRIPTIONS ..................................................24 2.2.1 SystemInterfaceSignals............................................24 2.2.2 PCIInterfaceSignals...............................................26 2.2.3 MemoryControllerInterfaceSignals ...................................29 2.2.4 VideoInterfaceSignals .............................................30 2.2.5 Power,Ground,andNoConnectSignals................................32 2.2.6 InternalTestandMeasurementSignals ................................32 2.3 SUBSYSTEMSIGNALCONNECTIONS.......................................34 2.4 POWERPLANES.........................................................36 3.0 ProcessorProgramming.......................................... 38 3.1 COREPROCESSORINITIALIZATION........................................38 3.2 INSTRUCTIONSETOVERVIEW.............................................39 3.2.1 LockPrefix.......................................................39 3.3 REGISTERSETS.........................................................40 3.3.1 ApplicationRegisterSet.............................................40 3.3.2 SystemRegisterSet ...............................................44 3.3.3 ModelSpecificRegisterSet..........................................59 3.3.4 TimeStampCounter ...............................................59 3.4 ADDRESSSPACES.......................................................60 3.4.1 I/OAddressSpace.................................................60 3.4.2 MemoryAddressSpace.............................................60 3.5 OFFSET,SEGMENT,ANDPAGINGMECHANISMS .............................61 3.6 OFFSETMECHANISM ....................................................61 3.7 DESCRIPTORSANDSEGMENTMECHANISMS................................62 3.7.1 Real and Virtual 8086 Mode Segment Mechanisms . ...............62 3.7.2 SegmentMechanisminProtectiveMode................................63 3.7.3 GDTRandLDTRRegisters..........................................66 3.7.4 DescriptorBitStructure .............................................67 3.7.5 GateDescriptors ..................................................69 3.8 MULTITASKINGANDTASKSTATESEGMENTS................................70 3.9 PAGINGMECHANISM.....................................................72 Revision 3.1 3 www.national.com Table of Contents (Continued) 3.10 INTERRUPTSANDEXCEPTIONS...........................................74 3.10.1 Interrupts ........................................................74 3.10.2 Exceptions.......................................................74 3.10.3 InterruptVectors...................................................75 3.10.4 InterruptandExceptionPriorities......................................76 3.10.5 ExceptionsinRealMode............................................77 3.10.6 ErrorCodes ......................................................77 3.11 SYSTEMMANAGEMENTMODE ............................................78 Geode™ GXm Processor 3.11.1 SMMEnhancements ...............................................79 3.11.2 SMMOperation ...................................................79 3.11.3 TheSMI#Pin.....................................................80 3.11.4 SMMConfigurationRegisters ........................................80 3.11.5 SMMMemorySpaceHeader.........................................80 3.11.6 SMMInstructions..................................................82 3.11.7 SMMMemorySpace...............................................83 3.11.8 SMIGeneration ...................................................83 3.11.9 SMIServiceRoutineExecution.......................................83