Design of a Broadband Signal Generation Platform for Fifth Generation (5G) Mobile Networks and Attocell Applications Hannes Ramon Supervisors: Dr. ir. Guy Torfs, Prof. dr. ir. Johan Bauwelinck Counsellor: Haolin Li Master's dissertation submitted in order to obtain the academic degree of Master of Science in Electrical Engineering Department of Information Technology Chairman: Prof. dr. ir. Daniël De Zutter Faculty of Engineering and Architecture Academic year 2014-2015 Design of a Broadband Signal Generation Platform for Fifth Generation (5G) Mobile Networks and Attocell Applications Hannes Ramon Supervisors: Dr. ir. Guy Torfs, Prof. dr. ir. Johan Bauwelinck Counsellor: Haolin Li Master's dissertation submitted in order to obtain the academic degree of Master of Science in Electrical Engineering Department of Information Technology Chairman: Prof. dr. ir. Daniël De Zutter Faculty of Engineering and Architecture Academic year 2014-2015 Preface This master thesis has been a real learning school where the complete design cycle for RF design has been undertaken. The design of a mixed signal RF front-end comes with many at first unexplainable and parasitic effects, which requires out of the box thinking and in most of the cases experience in the matter at hand. I want to thank my supervisors dr. ir. Guy Torfs and prof. dr. ir. Johan Bauwelinck first of all for making it possible for me to execute this thesis, but also for providing support with their experience and know-how in mixed signal RF design. The help of my counsellor ir. Haolin Li and other members of the INTEC Design group, such as ir. Timothy De Keulenaer and ir. Arno Vyncke, was also much appreciated. Designing a complex system requires a lot of testing before actually designing the final system. The fabrication of these testing PCBs was not possible without the PCB milling machine of ing. Jan Gillis and I want to thank him for taking his time and fabricating my boards. He also double checked my PCB layout of the design for possible flaws and provided valuable insight in the PCB design flow. Next I want to thank the department INTEC Design for putting their tools and measuring equipment at my disposal. During the complete year, talking to my friends and colleagues about the thesis was sometimes a real relief. This thank you goes to some friends to whom I spoke daily about this thesis: Jelle Bailleul, Laurens Bogaert, Gilles Bonne, Matthias Dewilde, Joris Lambrecht, Bob Mertens, Stef Vandermeeren, Zeger Van de Vannet and Johannes Van Wonterghem. Last but not least I also want to thank my family for their support and endless listening to me while explaining my thoughts. Hannes Ramon, May 2015 i Permission to consult The author gives permission to make this master dissertation available for consultation and to copy parts of this master dissertation for personal use. In the case of any other use, the copyright terms have to be respected, in particular with regard to the obligation to state expressly the source when quoting results from this master dissertation. Hannes Ramon, May 2015 ii Design of a Broadband Signal Generation Platform for Fifth Generation (5G) Mobile Networks and Attocell Applications by Hannes Ramon Master's dissertation submitted in order to obtain the academic degree of Master of Science in Electrical Engineering Academic Year 2014-2015 Supervisors: Dr. ir. Guy Torfs, Prof. dr. ir. Johan Bauwelinck Counselor: Haolin Li Department of Information Technology Chairmain: Prof. dr. ir. Dani¨elDe Zutter Faculty of Engineering and Architecture Universiteit Gent Abstract With the rise of 5G mobile networks and attocell applications, the need for higher bandwidth signal generation platforms ever increases. Current software defined radios only offer a couple of 10 MHz RF bandwidth, while for these new applications hundreds of MHz would be necessary. In this master thesis, a broadband (500 MHz) signal generation platform is developed further enable research in the 5G and attocell domain. This platform can be divided into two main parts: a digital design with a powerful FPGA followed by a mixed signal RF front-end. The mixed signal RF front-end consists of a powerful high speed DAC, followed by an I/Q modulator which mixes to 5.5 GHz. The required low jitter clocks and local oscillator are generated on the board. With respect to the digital part on the FPGA, a 5/6 resample filter is designed for convenient pulse shaping and predistortion filtering. Keywords Signal generation, FPGA, mixed-signal, RF, digital filter, 5G Design of a Broadband Signal Generation Platform for Fifth Generation (5G) Mobile Networks and Attocell Applications Hannes Ramon Supervisor(s): Dr. ir. Guy Torfs, prof. dr. ir. Johan Bauwelinck Abstract—With the rise of 5G mobile networks and attocell applications, 5th order low pass Chebychev-I ( = 0.5 dB) (differential) filter the need for higher bandwidth signal generation platforms ever increases. with cut-off frequency of 250 MHz. The filters directly connect Current software defined radios only offer a couple of 10 MHz RF band- width, while for these new applications hundreds of MHz would be neces- to the I/Q modulator (LTC5588) for upconversion to 5.5 GHz. sary. In this master thesis, a broadband (500 MHz) signal generation plat- This LO is generated by the synthesizer (LTC6948-4) which re- form is developed further enable research in the 5G and attocell domain. ceives the PLL reference from the clock generator (AD9516-4). This platform can be divided into two main parts: a digital design with a In addition, the clock generator also provides the 600 MHz DAC powerful FPGA followed by a mixed signal RF front-end. The mixed signal RF front-end consists of a powerful high speed DAC, followed by an I/Q and FPGA clock. Both the synthesizer and clock generator need modulator which mixes to 5.5 GHz. The required low jitter clocks and lo- to have a low phase noise output to minimize distortion. cal oscillator are generated on the board. With respect to the digital part on the FPGA, a 5/6 resample filter is designed for convenient pulse shaping B. Layout and predistortion filtering. Keywords—Signal generation, FPGA, mixed-signal, RF, digital filter, 5G Mixed signal PCB design requires careful routing and place- ment of the components. Fig. 2 shows a schematic representa- tion of the component placement and the most important con- I. INTRODUCTION nections on the PCB. The digital components (clock and DAC) EW wireless communication systems require a much are on the left, while the other analog components are placed Nhigher bandwidth due to the higher bitrate needed. Cur- on the right side of the board to minimize the interference be- rent software defined radios only provide a couple of 10 MHz, tween the noisy digital signals and the sensitive analog signals but in order to deliver Gb/s wireless links to the users, a band- and components. width of a factor 10 higher (in the order of 100 MHz) should be Clk in needed. To enable research in this domain, a broadband signal Clk out generation platform around a powerful Kintex-7 FPGA is de- signed. It consists of two parts: a digital design on the FPGA clock I/Q mod. RF amplifier and an analog front-end. This platform was specified to have a 500 MHz RF bandwidth and an output frequency range of 5 to FPGA clk I-filter 6 GHz. DAC 16 bit LVDS RF out II. DESIGN OF THE ANALOG FRONT-END FMC connector Q-filter A. System architecture synthesizer The analog front-end consists of a DAC (Digital-to-Analog converter), anti-imaging filters, an I/Q modulator and a RF am- Fig. 2. Schematic representation of the component placement plifier. The common clock is provided by a clock manager and the LO (local oscillator) is generated by a synthesizer. Fig. 1 shows a block diagram of the system architecture. III. DESIGN OF DIGITAL RESAMPLING FIR FILTER A. Introduction I I I FPGA Q DAC Q Q + G The 500 MHz RF BW limits the symbol rate to 500 Mbaud, but the clock speed of the DAC is 600 MHz to enable a 1.1 over- sampling ratio. To convert the 500 MSPS (pulseshaped sym- Clock generator Synthesizer bols) to 600 MSPS for digital-to-analog conversion a general Fig. 1. System architecture digital resample filter with factor 1.1 is designed. B. Topology The DAC (AD9122) receives the digital signals I and Q sam- pled at 600 MHz and performs a digital to analog conversion Traditional resampling is performed by upsampling to the creating two analog signals I and Q that are filtered to remove lowest common multiple of both symbol rates, which is 3 GHz the images introduced by the conversion. The analog filter is a in this case. This 3 GHz signal is downsampled to 600 MHz. The FPGA cannot handle the 3 GHz signal and by observing −50 that most of the upsampling operations actually are zero oper- −60 ations, the upsampling is split into 6 parallel lower rate (500 −70 MHz) filters (filter 1 to 6) [1]. By performing a parallel to serial −80 conversion on these 6 filters, the 3 GHz signal is reconstructed. −90 When decimating directly on these 6 parallel outputs, only one −100 Phase noise [dBc/Hz] filter is active at each clock cycle and a multiplier reduction of −110 6 can be performed when reusing the multipliers and adders. To −120 solve timing problems with the fast 600 MHz clock, the filter −130 2 3 4 5 6 10 10 10 10 10 is split into 2 Filter streams (indicated with capital F), Filter 1 Frequency offset [Hz] (contains filter 1, filter 5 and 3) and Filter 2 (contains filter 6, Fig.