University of Kentucky UKnowledge University of Kentucky Master's Theses Graduate School 2009 VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS David Allen Crutchfield University of Kentucky, [email protected] Right click to open a feedback form in a new tab to let us know how this document benefits ou.y Recommended Citation Crutchfield, David Allen, "VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS" (2009). University of Kentucky Master's Theses. 631. https://uknowledge.uky.edu/gradschool_theses/631 This Thesis is brought to you for free and open access by the Graduate School at UKnowledge. It has been accepted for inclusion in University of Kentucky Master's Theses by an authorized administrator of UKnowledge. For more information, please contact [email protected]. ABSTRACT OF THESIS VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS Verification and debug of integrated circuits for embedded applications has grown in importance as the complexity in function has increased dramatically over time. Various modeling and debugging techniques have been developed to overcome the overwhelming challenge. This thesis attempts to address verification and debug methods by presenting an accurate C model at the bit and algorithm level coupled with an implemented Hardware Description Language (HDL). Key concepts such as common signal and variable naming conventions are incorporated as well as a stepping function within the implemented HDL. Additionally, a common interface between low-level drivers and C models is presented for early firmware development and system debug. Finally, self- checking verification is discussed for delivering multiple test cases along with testbench portability. KEYWORDS: C Modeling, Hardware Description Language, Verification, Debug, Testbench Portability David Crutchfield November 20, 2009 VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS By David Allen Crutchfield Dr. Bruce Walcott Director of Thesis Dr. Stephen Gedney Director of Graduate Studies November 20, 2009 RULES FOR THE USE OF THESIS Unpublished thesis submitted for the Master’s degree and deposited in the University of Kentucky Library are as a rule open for inspection, but are to be used only with due regard to the rights of the authors. Bibliographical references may be noted, but quotations or summaries of parts may be published only with the permission of the author, and with the usual scholarly acknowledgments. Extensive copying or publication of the thesis in whole or in part also requires the consent of the Dean of the Graduate School of the University of Kentucky. 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Name Date ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ THESIS David Allen Crutchfield The Graduate School University of Kentucky 2009 VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS THESIS A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering at the University of Kentucky By David Allen Crutchfield Georgetown, Kentucky Director: Dr. Bruce Walcott, Professor of Electrical Engineering Lexington, Kentucky 2009 Copyright© David Allen Crutchfield 2009 ACKNOWLEDGEMENTS I want to thank Dr. Bruce Walcott, my advisor and friend, for his support throughout this process. Despite my ineffectiveness in choosing a path and completing the project in a timely fashion, he continued to motivate and encourage me. Even when I waited until literally the last hour, he helped me through several administrative hoops in the end. I am deeply indebted to Dr. Walcott for getting me to this point in both my graduate and undergraduate studies. His influence can be seen not only in my life, but also in the lives of others. I want to thank Dr. J. Robert Heath for serving on my committee and for all his support during my undergraduate studies. His influence has helped shape my desire for logic design and embedded microcontroller applications. I want to also thank Dr. YuMing Zhang for serving on my committee. Next, I would like to thank several of my colleagues at Lexmark for their support at the final hour. I would like to thank Chris Case, James Sharpe and Zach Fister for taking extra time from their busy lives to read an unpolished version of this thesis and give critical and constructive feedback. I respect their talents and look forward to many more years as their co-worker. I am grateful for my family and their support. My mother, Margaret Gilbert, instilled the desire to overachieve and pursue my dreams. I am thankful to her for that and for her love. Obviously, I could not have done this without my beautiful wife, Brandy. I thank her for being patient and loving after so many years and taking the boys away for that pivotal week. Without the solitude I could have never pulled this off. Lastly, I want to thank my Lord and Savior Jesus Christ in whom all things are possible. iii TABLE OF CONTENTS Acknowledgements............................................................................................................iii List of Figures..................................................................................................................... v Chapter 1: Introduction....................................................................................................... 1 Chapter 2: Background Research........................................................................................ 3 Chapter 3: Problem Statement .......................................................................................... 16 Chapter 4: Modeling and Verification of Error Diffusion Using C Model ...................... 20 Chapter 5: Using the Error Diffusion C Model ................................................................ 41 Chapter 6: Future Work .................................................................................................... 55 References......................................................................................................................... 57 iv LIST OF FIGURES Figure 2.1: Simulation-based RTL Verification Flow Using System-level Models [10]. 12 Figure 2.2: Conceptual Design Flow of a Digital System [12]......................................... 13 Figure 2.3: Simplified Model of the Object Based Interface [14]. ................................... 14 Figure 2.4: The Role of the Transactor in Testbench Verification [25]. .......................... 15 Figure 4.1: Effect of Error Spreading on Neighboring Pixels. ......................................... 29 Figure 4.2: C Model Excerpt of LFSR Function. ............................................................. 30 Figure 4.3: C Model Excerpt for Duplication of LFSR Function..................................... 31 Figure 4.4: C Model Excerpt of Implemented Running Pixel Calculation....................... 32 Figure 4.5: HDL Excerpt of Implemented Running Pixel Calculation. ........................... 32 Figure 4.6: C Model Excerpt of DiffParamsStruct. .......................................................... 33 Figure 4.7: Implemented HDL Firmware Specification Excerpt for LFSR Function..... 34 Figure 4.8: Main Control Register Firmware Specification Excerpt................................ 35 Figure 4.9: Portion of Controlling State Machine Driven by Signal WAIT_ST.............. 36 Figure 4.10: Excerpt of Implemented HDL for WAIT_ST Assignment.......................... 36 Figure 4.11: Firmware Specification Excerpt Showing STATE_SIGS Access. .............. 37 Figure 4.12: Encapsulated Verification System Utilizing an Accurate C Model............. 38 Figure 4.13: System Architecture Incorporating Bus Model............................................ 39 Figure 4.14: Sample Simple Script for Bus Model Stimulus............................................ 40 Figure 5.1: Diffused Image Using Accurate C Model...................................................... 47 Figure 5.2: Diffused Image Using Altered C Model. ....................................................... 48 Figure 5.3: Diffused Image Using Accurate C Model...................................................... 49 Figure 5.4: Diffused Image Using Altered C Model. ....................................................... 49 v Figure 5.5: Simulation Wave vs. C Model Debugger at First Pixel. ................................ 50 Figure 5.6: Simulation Wave vs. C Model Debugger at Fourth Pixel.............................. 51 Figure 5.7: Simulation Wave vs. C Model Debugger at Fifth Pixel................................. 52 Figure 5.8: Simulation Wave vs. C Model Debugger with Corrected LFSR at First Pixel. ................................................................................................................................... 53 Figure