ANTAIOS Datasheet ANT1000/1001 | Revision 1.26 Liability Exclusion We have tested the contents of this document regarding agreement with the hardware and software described. Nevertheless, there may be deviations and we do not guarantee complete agreement. The data in the document is tested periodically, however. Required corrections are included in subsequent versions. We gratefully accept suggestions for improvements. Copyright Copyright © YASKAWA Europe GmbH 2021. All Rights Reserved. Unless permission has been expressly granted, passing on this document or copying it, or using and sharing its content are not allowed. Offenders will be held liable. All rights re- served, in the event a patent is granted or a utility model or design is registered. This document is subject to changes without prior notice. ANT1000/1001 Datasheet Revision 1.26 2/152 Copyright © YASKAWA Europe GmbH, 2021 Table of Contents 1 Overview ........................................................................................ 11 2 Block Diagram ............................................................................... 12 3 Key IPs and Features .................................................................... 13 3.1 ARM Cortex-A5 CPU Core ...................................................................................13 3.2 Advanced Real-Time Ethernet Switch ..................................................................13 3.3 Integrated 100Base-TX Ethernet PHYs (2x) .........................................................14 3.4 SNAP+ (SliceBus) Master ....................................................................................14 3.5 Gigabit Ethernet MAC ...........................................................................................15 3.6 DDR2 SDRAM Controller (16-bit) .........................................................................15 3.7 Asynchronous External Interface (AEI) .................................................................16 3.8 FIFO Interface ......................................................................................................16 3.9 Consistency Interface (CI) ....................................................................................16 3.10 PROFIBUS DP Master (2x) ..................................................................................16 3.11 VPC3+ PROFIBUS DP Slave ...............................................................................17 3.12 CAN Interface (2x) ................................................................................................17 3.13 NAND Flash Controller .........................................................................................17 3.14 QuadSPI Interface ................................................................................................17 3.15 SD/MMC Card Controller ......................................................................................18 3.16 USB 2.0 Device Controller ....................................................................................18 3.17 Advanced IRQ Controller ......................................................................................18 3.18 Main DMA Controller ............................................................................................18 3.19 AHB/APB Bridge (2x) ...........................................................................................18 3.20 SPI Interface ........................................................................................................19 3.21 UART (2x) ............................................................................................................19 3.22 I²C Interface .........................................................................................................20 3.23 Timer and Watchdog Module ................................................................................20 3.24 Boot Code ............................................................................................................20 3.25 Technology Function Module (TechIO) .................................................................21 4 Application Details ........................................................................ 22 4.1 Bootloader ............................................................................................................22 4.2 eCos .....................................................................................................................23 4.3 eCos Drivers (Board Support Package) ................................................................24 4.4 Deliverables (eCos, toolchain) by profichip ...........................................................24 4.5 EtherCAT Slave ....................................................................................................25 4.5.1 Requirements Hardware ........................................................................... 25 4.5.2 Requirements Software ............................................................................. 25 4.6 PROFINET Device ...............................................................................................26 4.7 Ethernet PHYs ......................................................................................................27 4.7.1 Qualified Chips .......................................................................................... 28 4.8 SliceBus Interface ................................................................................................28 4.8.1 Qualified Chips .......................................................................................... 28 ANT1000/1001 Datasheet Revision 1.26 3/152 Copyright © YASKAWA Europe GmbH, 2021 Table of Contents 4.9 Gigabit Ethernet Interface .....................................................................................28 4.9.1 Qualified Chips .......................................................................................... 28 4.10 DDR2 Memory ......................................................................................................28 4.10.1 64 MByte Configuration (1 chip) ................................................................ 28 4.10.2 128 MByte Configuration (2 chips) ............................................................ 28 4.10.3 128 MByte Configuration (1 chip) .............................................................. 28 4.10.4 256 MByte Configuration (2 chips) ............................................................ 29 4.10.5 Qualified Chips .......................................................................................... 29 4.11 Asynchronous External Interface (AEI) .................................................................29 4.11.1 SRAM Master Mode: Port D Mode V1 ....................................................... 29 4.11.1.1 Qualified Chips ............................................................................29 4.11.2 SRAM Slave Interface: Port D Mode V2 .................................................... 29 4.12 Asynchronous/SDR NAND Flash..........................................................................29 4.12.1 Qualified Chips .......................................................................................... 29 4.13 QuadSPI NOR Flash ............................................................................................30 4.13.1 Up to 128 Mbit Configuration ..................................................................... 30 4.13.2 Beyond 128 Mbit Configuration ................................................................. 30 4.13.3 2 Chip Configuration ................................................................................. 30 4.13.4 Qualified Chips .......................................................................................... 30 4.14 SPI Slave Connection ...........................................................................................30 4.15 SPI Master Connection .........................................................................................30 4.16 I²C Interface .........................................................................................................31 4.16.1 Qualified Chips .......................................................................................... 31 4.17 JTAG Debug Interface ..........................................................................................31 4.18 ETM Trace Output ................................................................................................31 4.18.1 16-bit Output ............................................................................................. 31 4.18.2 32-bit Output ............................................................................................. 31 5 Pin Description .............................................................................. 33 5.1 Pinout ...................................................................................................................33 5.1.1 TFBGA-380 ............................................................................................... 34 5.1.2 TFBGA-385 ............................................................................................... 38 5.2 Pin Assignment ....................................................................................................42 5.2.1 General statements and notes .................................................................. 42 5.2.2 Power / Ground ........................................................................................