A Memristive Dynamic Adaptive Neural Network Array (mrDANNA) Garrett S. Rose, PhD [email protected] March 9, 2016 Overview ● Memristive Neuromorphic Systems: Where we've been – Memristor basics – Programmable Threshold Logic Arrays – Gradient descent for memristive circuits ● Memristive Neuromorphic Systems: Where we're going – Background: The NIDA/DANNA architecture – Reconfigurable structure in memristive neuromorphic systems – mrDANNA: a Memristive Dynamic Neural Network Array 2 Overview ● Memristive Neuromorphic Systems: Where we've been – Memristor basics – Programmable Threshold Logic Arrays – Gradient descent for memristive circuits ● Memristive Neuromorphic Systems: Where we're going – Background: The NIDA/DANNA architecture – Reconfigurable structure in memristive neuromorphic systems – mrDANNA: a Memristive Dynamic Neural Network Array 3 The Memristor ● A “fundamental device device property”: memristance ● A memristor (“memory resistor”) similar to variable resistor that can be made to operate in one of many states ● Many interesting applications: nanoscale digital logic, memory (next- gen Flash), neuromorphic computing 4 Hafnium-Oxide Memristors ● SUNY Polytechnic—CNSE fabricating HfO2 memristors ● Complete hybrid CMOS/memristor process – Memristors in via layer between metal1 and metal2 Ref.: N. Cady, et al., “Towards Memristive Dynamic Adaptive Neural Network Arrays,” GOMAC, March 2016. 5 Prior Work: Memristive Programmable Threshold Gate Array ● Threshold logic a natural fit for memristive circuits ● Memristors are used as “artificial synapses” ● CMOS can be used as neurons Ref.: J. Rajendran et al., “Memristor-based Prog. Threshold Logic Array,” NANOARCH, 2010. 6 All Nano Memristive Gate Array ● Memristors used as weights in programmable threshold gates ● Resonant tunneling diodes used to construct Goto pair latches – Provides gain and acts as thresholding circuit Ref.: G.S. Rose et al., “Leveraging Memristive Systems in Construction of Digital Logic,” Proc of IEEE, 2012. All Nano Memristive Gate Array ● Memristors used as weights in programmable threshold gates ● Resonant tunneling diodes used to construct Goto pair latches – Provides gain and acts as thresholding circuit RTD+Memristor Basic Shape Classification Ref.: G.S. Rose et al., “Leveraging Memristive Systems in Construction of Digital Logic,” Proc of IEEE, 2012. Training a Threshold Gate Array ● Supervised learning based on stochastic gradient descent ● “Read-monitored-write” approach with incremental changes in memristance ● Hardware still built with global and local training circuits Ref.: H. Manem et al., “Stochastic Gradient Descent for CMOS/Memristive Threshold Gate Array,” TCAS-I, 2012. 9 Overview ● Memristive Neuromorphic Systems: Where we've been – Memristor basics – Programmable Threshold Logic Arrays – Gradient descent for memristive circuits ● Memristive Neuromorphic Systems: Where we're going – Background: The NIDA/DANNA architecture – Reconfigurable structure in memristive neuromorphic systems – mrDANNA: a Memristive Dynamic Neural Network Array 10 NIDA: Neuro-Inspired Dynamic Architecture ● Spiking neural network embedded in 3D space ● Simple neuron and synapse design: 2 parameters per element ● Discrete event simulation Ref.: C. Schuman, J.D. Birdwell, and M. Dean, “Neuroscience-Inspired Dynamic Architectures,” BSEC, 2014. 11 Dynamic Adaptive Neural Network Array (DANNA) ● Array of programmable neural network elements ● Each element can be connected to up to 16 other elements ● Have implemented using FPGA ● Hardware-accurate simulator available – used for offline evolutionary optimization Ref.: M. Dean, C. Schuman, and J.D. Birdwell, “Dynamic Adaptive Neural Network Array,” Springer, 2014. 12 NIDA/DANNA Results – Iris Dataset Toward a Memristive DANNA (mrDANNA) ● Maintain salient features of NIDA/DANNA architecture: – Configurable hardware: structure & weights optimized offline – Dynamic adaptation via LTD/LTP mechanism – Simple neuron and synapse design ● Neurons: programmable threshold & refractory period ● Synapses: programmable delay & synaptic weights ● Leverage metal-oxide memristors for synapses – High density synaptic arrays – Potential for low-power operation Goal: A memristor-based neuromorphic system with reconfigurable structure, parameter initialization and dynamic adaptability. 14 mrDANNA Circuit Elements • Memristors for synaptic weights • Neuron follows integrate-and-fire • Memristance (memristor resistance) always mechanism positive – one memristor can only represent • Integrator accumulates charge to reach positive weight threshold in integration phase • Pair of memristors used to represent either • Comparator and “firing flop” generate firing positive or negative weight spike during firing phase • One memristor (Rp) drives positive current; • When firing, integrator charge clears other (Rn) negative current • Feedback to synaptic inputs for potentiation/depression during firing Rp < Rn → positive weight Rp > Rn → negative weight 15 LTP and LTD in mrDANNA System ● Implemented NIDA rule for LTP/LTD ● LTP: Increase weight for synapse causing a post-synaptic neuron firing event ● LTD: Decrease weight for synapse that fires simultaneous to post- synaptic neuron firing event ● Integrate & Fire neurons – integrates until threshold reached, charge resets upon firing event 16 Simple Example: Pattern Recognition of Very Basic Images ● Four images: 0 0 1 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 – Triangle 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 – Square 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 1 1 – Diamond 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 – Plus 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 ● Circuit tested using both pure and noisy images ● Up to 3 noise bits generated randomly ● Functional weight matrix – base of network structure é----3 1 1 1 3 ù ê ú ● 1 3 1 3 1 Determining the weight matrix – difference between ê--- ú weighted triangle image matrix and all others ê---3 3 1 3 3 ú ● Simple network allows easy assessment of memristive ê ú 3--- 1 3 1 3 synapses and neurons ê ú ëê3 3 1 3 3 ûú Functional Weights 17 Simulation Results • Each column of weight matrix denotes the weights of each neuron • Optimization of number of neurons reduces the structure complexity • Threshold calculation consistent with maximum and minimum synaptic weights 18 Moving Forward: Circuit & Architecture Refinement ● Build better understanding of constraints for memristive circuits – Guide any needed algorithmic refinement ● Optimize peripheral circuitry for initializing memristive elements ● Hardware interfaces and software – Developing FPGA-based DANNA in parallel – improved interfaces – Software: Evolutionary optimization, mrDANNA simulator, “commander” and other tools for interfacing with the system ● Strike a balance: offline network initialization vs. online training ● Far term consideration: – Nanoscale RTD-based neurons? 19 Summary ● Memristors essentially artificial synapses ● Straightforward implementations of threshold logic possible ● Depending on materials used, memristors offer low power operation with reasonable delay ● Developing memristive dynamic adaptive neural network array (mrDANNA) 20 Acknowledgements ● Collaborators: ● Students: – Nathaniel Cady (CNSE) – Gangotree Chakma – Joseph Van Nostrand (AFRL) – Mesbah Uddin – Mark Dean (UTK) – Adam Disney – James Plank (UTK) – Patricia Eckhart – Catherine Schuman (ORNL) – John Reynolds – Thomas Potok (ORNL) – Austin Wyer – Robert Patton (ORNL) – Elvis Offor – Steven Young (ORNL) – Miles Gepner – Daniel Caballero ● Sponsors:.