USOO7768754B2 (12) United States Patent (10) Patent No.: US 7,768,754 B2 Collins, III et al. (45) Date of Patent: Aug. 3, 2010 (54) CERAMICSUBSTRATE FOR LIGHT 4,506,285 A 3/1985 Einzinger EMITTING DODE WHERE THE SUBSTRATE 5,176,772 A 1, 1993 Ohtaki NCORPORATES ESD PROTECTION 5,235,310 A 8, 1993 Cowman et al. 5,290,375 A 3/1994 Nagasaka et al. (75) Inventors: William David Collins, III, San Jose, 5,540,884 A 7, 1996 Chiao CA (US); Jerome Chandra Bhat, San 5,874,378 A 2/1999 Ishida et al. Francisco, CA (US) 5,889.308 A 3/1999 Hong et al. (73) Assignees: Philips Lumileds Lighting Company, 6,217,990 B1 4/2001 Asai et al. LLC, San Jose, CA (US); Koninklijke 6,339,367 B1 1/2002 Takehana Philips Electronics N.V., Eindhoven 6,535,105 B2 3/2003 Heistand, II et al. (NL) 2001/0043454 A1 11/2001 Yoshii et al. 2002/0179914 A1 12/2002. Sheu (*) Notice: Subject to any disclaimer, the term of this 2003/0043013 A1 3/2003 Shiraishi et al. patent is extended or adjusted under 35 2004/0222433 A1* 11/2004 MaZZochette et al. ......... 257/99 U.S.C. 154(b) by 402 days. (21) Appl. No.: 11/848,055 (22) Filed: Aug. 30, 2007 OTHER PUBLICATIONS O O Lionel M. Levinson et al., “The physics of metal Oxide Varistors'. (65) Prior Publication Data Journal of Applied Physics, vol. 46, No.3, Mar. 1975, pp. 1332-1341. US 2007/O297.108A1 Dec. 27, 2007 Mark Drabkin et al., “Improved Metal Oxide Varistor Packaging Technology For Transient Voltage Surge Suppressers (TVSS)”. Related U.S. Application Data Improved MOV Packaging Technology for TVSS document, pp. 1-14. (63) Continuation of application No. 10/787,657, filed on Feb. 25, 2004, now Pat. No. 7,279,724. (Continued) (51) Int. Cl Primary Examiner Kenneth A Parker iotL 29/22 (2006.01) Assistant Examiner Joseph Nguyen HOIL 29/24 (2006.01) 57 ABSTRACT (52) U.S. Cl. ............................. 361/56; 257/98; 257/99; (57) 257/100 (58) Field of Classification Search .......) - - - - - - - - - - - . A metal oxide varistor comprising one or more Zinc oxide S lication file f 1 257 2. 338/21 layers is formed integral to a ceramic Substrate to provide ee application file for complete search history. ESD protection of a semiconductor device mounted to the (56) References Cited substrate. The portion of the ceramic substrate not forming the varistor may be aluminum oxide, aluminum nitride, sili U.S. PATENT DOCUMENTS con carbide, or boron nitride. The varistor portion may form 3.679,950 A T. 1972 Rutt any part of the ceramic Substrate, including all of the ceramic 3,725,836 A 4, 1973 Wada et al. substrate. 3,743,897 A 7/1973 Harnden, Jr. 3,965,552 A 6, 1976 Rutt 10 Claims, 5 Drawing Sheets ENCAPSULATING SILICONE OR EPOXY 3O WITH OPTIONAL PHOSPHOR LOADING ; SOLDER OR AU 23 INTERCONNECT 18 14 TOPSIDE THROUGH METALLIZATION METALLIZATION A2 42 BASIDE.22 Varistor 40 22 ASINKE40 METALLIAATION(SODERABLE, METALIZATIONS US 7,768,754 B2 Page 2 OTHER PUBLICATIONS “Mulilayer Varistor Over Voltage Protector'. Internet paper down Naoki Ohashi et al., “Synthesis of zinc oxide varistors with a break loaded on Dec. 11, 2003 from http://www.spkecl.com/htdoc? down voltage of three volts using an intergranular glass phase in the multilayer-varistor-over-voltage-protector.htm, pp. 1-3. bismuth-boron-oxide system”, Internet article downloaded on Dec. TransientVoltage Suppressors, AVX TransGuard R. paper, pp. 1-13. 11, 2003 from ttp://content.aip.org/APPLAB/v83//i23/4857 1. html, 1 page * cited by examiner U.S. Patent Aug. 3, 2010 Sheet 1 of 5 US 7,768,754 B2 ENCAPSULATING SILICONE OR EPOXY 10 WITH OPTIONAL PHOSPHOR LOADING SOLDER OR AU INTER CONNECT 23 18 LED MEston The 14 14 MEion BAC,22 SIDE CERAMIC 22 (SOLDERABLE) METALLIZATION (PRIOR ART) CURRENT ELECTRODES 21 W/-4-272.5 ZnO GRAN S5C27 INTERGRANULAR ZZA MATERAL 22/222a2aaaaaaa22222222aaaaaa 28 FIG.2 (PRIOR ART) U.S. Patent Aug. 3, 2010 Sheet 2 of 5 US 7,768,754 B2 ENCAPSULATING SLICONE OR EPOXY 30 WITH OPTIONAL PHOSPHOR LOADING SOLDER OR AU INTER CONNECT 18 14 TOPSIDE THROUGH METALLIZATION METALLIZATION 42 42 BACKSIDE22 Varison 40 22 ALLUMINUM/BORON40 (SOLDERABLE) METALLIZATIONS OXIDE/NITRIDE, SIC METALLIZATION SOLDER OR AU 12 INTERCONNECT LED NXYet, 54-xNeyyye se/DOPED) ZINCOXIDE 56 WRAP-AROUND METALLIZATION WARISTOR METALLIZATIONS FIG. 4 U.S. Patent Aug. 3, 2010 Sheet 3 of 5 US 7,768,754 B2 MOLDED LENS WREBOND 66 WagoND DE ATTACH EPOXY REFLECTOR WALLS 63 64 40-N 1622NXN 2S 42- SGGSise 42 40 ENCAPSULATING SILICONE OR EPOXY WITH OPTIONAL PHOSPHOR LOADING 23 SOLDER OR AU INTER CONNECT 18 TOPSIDE 54 METALLIZATION a SeNAN NaNetix VARISTOR- Nes METALLIZATIONS (DOPED) 22 42 72 ZNC OXDE BACKSDE ALLUMINUM/BORON 42 (SOLDERABLE). OXDE/NITRIDESC TOPSIDE METALLIZATION METALLIZATION FIG. 6 U.S. Patent Aug. 3, 2010 Sheet 4 of 5 US 7,768,754 B2 SOLDER OR AU (DOPED) INTER CONNECT ZNC OXDE 18 70 XXXXXXXXXXXXXXXXX DXO XOX X XXOX 14 X X XX X X X g X XXXXXXXXXXXXXXXXXC ALUMINUM/BORON OXIDE/NITRIDE, SIC FIG.7 23 22 22 U.S. Patent Aug. 3, 2010 Sheet 5 of 5 US 7,768,754 B2 84 VARISTOR SECTION 90 ZZZZZZZYZZYZZYZZYZZYZZ ZZZZYZZYZZZZZZYZZYZZY METALLIZATION 74 22 ALUMINUMNITRIDE, OR OXIDE, OR BORON NITRIDE, SIC F.G. 10 US 7,768,754 B2 1. 2 CERAMIC SUBSTRATE FOR LIGHT the need for forming the ESD protection circuitry on the chip EMITTING DODE WHERE THE SUBSTRATE or providing a separate ESD protection circuit in the package NCORPORATES ESD PROTECTION or external to the package. BRIEF DESCRIPTION OF THE DRAWINGS CROSS REFERENCE TO RELATED 5 APPLICATIONS FIG. 1 is a cross-sectional view of a prior art surface mounted LED package. This application is a continuation of application Ser. No. FIG. 2 is a cross-sectional view of a typical metal oxide 10/787,657, filed Feb. 25, 2004 and incorporated herein by 10 Varistor comprising Zinc oxide grains. reference. FIG. 3 is a cross-sectional view of an LED package incor porating a metal oxide varistor as an ESD protection circuit in FIELD OF INVENTION the central portion of the ceramic substrate. FIG. 4 is a cross-sectional view of another embodiment of an LED package where the varistor forms almost the entire This invention relates to electrostatic discharge (ESD) pro ceramic Substrate. tection of electronic devices and, more particularly, to ESD FIG. 5 is a cross-sectional view of an LED package where protection for a semiconductor chip (e.g., a light emitting the LED chip electrodes are connected with wires to a diode) mounted on a ceramic Substrate. ceramic Substrate incorporating a metal oxide varistor. FIG. 6 is a cross-sectional view of another embodiment of BACKGROUND 2O an LED package where the ceramic Substrate incorporates a metal oxide varistor around a periphery of the substrate. FIG. 1 is a cross-sectional view of a prior art light emitting FIG. 7 is a top-down view of the structure of FIG. 6. diode (LED) package 10. Package 10 contains an LED chip FIG. 8 is a cross-sectional view of another embodiment of 12 having cathode and anode contacts coupled, via metal 25 an LED package where the Substrate incorporates a Zinc interconnects 18, to metal pads 14 on a ceramic Substrate 16. oxide varistor as a top layer of the substrate and where the zinc Metal vias 20 extend through substrate 16 and contact back oxide is sandwiched between two varistor electrodes. side metal pads 22. The LED chip is encapsulated by epoxy FIG. 9 is a cross-sectional view of another embodiment of 23. Package 10 is typically solder-mounted onto a printed an LED package where the Substrate incorporates a Zinc circuit board or incorporated into another package. Such 30 oxide varistor as a top layer of the substrate and where the varistor electrodes are formed on a top surface of the Zinc other package typically includes a lens, reflective walls, a oxide layer. base, and leads. The various metal interconnects in combina FIG.10 is a cross-sectional view of another embodiment of tion with the ceramic substrate 16 conduct heat from the LED chip 12 to the printed circuit board, which may include an an LED package where the Substrate incorporates a Zinc 35 oxide varistor as a top layer of the Substrate along the outer additional heat sink. portions of the substrate. LEDs are well known and are formed from semiconductor materials on a substrate. The LED chip 12 substrate material DETAILED DESCRIPTION may be a semiconductor, a conductor, or an insulator. LEDs can be damaged by high voltages from ESD. It is 40 Ceramic Substrates are commonly used to provide a her common to provide ESD protection for an LED, such as metic Seal, electrical insulation, mechanical stability, and a providing a separate ESD protection circuit in the LED pack conductive heat path for integrated circuits. Ceramic Sub age or on the printed circuit board. Providing a separate ESD strates are easy to form by mixing ceramic powder in a binder protection circuit in the LED package may increase the size of and casting it into the desired form. The ceramic grains may 45 also be sintered under pressure to bind the grains together. the package and/or reduce the light-emitting area of the chip Suitable metal patterns are then deposited on the formed 12. Forming the ESD protection circuitry on the PC board or ceramic Substrate.