Roa Logic Silicon Proven IP for FPGA and ASIC www.roalogic.com RV12 RISC-V 32/64-bit CPU Core Datasheet (v1.3) http://roalogic.github.io/RV12 01-Feb-2018 c Roa Logic B.V. Contents 1 Product Brief1 1.1 Introduction....................................1 1.2 Features......................................2 2 Introduction to the RV123 2.1 Privilege Levels..................................3 2.2 Execution Pipeline................................3 2.2.1 Instruction Fetch (IF)..........................4 2.2.2 Instruction Pre-Decode (PD)......................5 2.2.3 Instruction Decode (ID).........................5 2.2.4 Execute (EX)...............................5 2.2.5 Memory (MEM).............................5 2.2.6 Write Back (WB)............................5 2.3 Branch Prediction Unit.............................5 2.4 Control & Status Registers (CSRs).......................6 2.5 Debug Unit....................................6 2.6 Data Cache....................................6 2.7 Instruction Cache.................................6 2.8 Integer Pipeline..................................7 2.9 Register File...................................7 3 RV12 Execution Pipeline8 3.1 Instruction Fetch (IF)..............................9 3.2 Pre-Decode (PD)................................. 10 3.3 Instruction Decode (ID)............................. 11 3.4 Execute (EX)................................... 13 3.5 Memory-Access (MEM)............................. 15 3.6 Write-Back (WB)................................. 16 4 Configurations 17 4.1 Introduction.................................... 17 4.2 Core Parameters................................. 17 4.2.1 JEDEC BANK and JEDEC MANUFACTURER ID......... 18 4.2.2 XLEN................................... 18 i RV12 RISC-V CPU Core (v1.3) Roa Logic 4.2.3 PC INIT................................. 19 4.2.4 PLEN................................... 19 4.2.5 PMP CNT................................ 19 4.2.6 PMA CNT................................ 19 4.2.7 HAS USER................................ 19 4.2.8 HAS SUPER............................... 19 4.2.9 HAS HYPER............................... 19 4.2.10 HAS RVM................................ 19 4.2.11 HAS RVA................................. 19 4.2.12 HAS RVC................................. 20 4.2.13 HAS BPU................................. 20 4.2.14 IS RV12E................................. 20 4.2.15 MULT LATENCY............................ 20 4.2.16 BPU LOCAL BITS........................... 20 4.2.17 BPU GLOBAL BITS.......................... 20 4.2.18 HARTID................................. 21 4.2.19 ICACHE SIZE.............................. 21 4.2.20 ICACHE BLOCK LENGTH...................... 21 4.2.21 ICACHE WAYS............................. 21 4.2.22 ICACHE REPLACE ALG....................... 21 4.2.23 DCACHE SIZE.............................. 21 4.2.24 DCACHE BLOCK LENGTH...................... 21 4.2.25 DCACHE WAYS............................. 22 4.2.26 DCACHE REPLACE ALG....................... 22 4.2.27 BREAKPOINTS............................. 22 4.2.28 TECHNOLOGY............................. 22 4.2.29 MNMIVEC DEFAULT......................... 22 4.2.30 MTVEC DEFAULT........................... 22 4.2.31 HTVEC DEFAULT........................... 23 4.2.32 STVEC DEFAULT............................ 23 4.2.33 UTVEC DEFAULT........................... 23 5 Control and Status Registers 24 5.1 Introduction.................................... 24 5.2 Accessing the CSRs................................ 24 5.3 Illegal CSR accesses............................... 25 ii RV12 RISC-V CPU Core (v1.3) Roa Logic 5.4 Timers and Counters............................... 25 5.5 CSR Listing.................................... 26 5.6 Machine Level CSRs............................... 28 5.6.1 Machine ISA Register (misa)...................... 28 5.6.2 Vendor ID Register (mvendorid).................... 29 5.6.3 Architecture ID Register (marchid).................. 29 5.6.4 Implementation ID Register (mimpid)................. 30 5.6.5 Hardware Thread ID Register (mhartid)................ 30 5.6.6 Machine Status Register (mstatus)................... 30 5.6.7 Privilege and Global Interrupt-Enable Stack in mstatus register.. 30 5.6.8 Base ISA Control in mstatus Register................. 31 5.6.9 Memory Privilege in mstatus Register................. 32 5.6.10 Machine Trap-Handler Base Address Register (mtvec)........ 32 5.6.11 Machine Delegation Registers (medeleg & mideleg)......... 33 5.6.12 Machine Interrupt Registers (mie, mip)................ 33 5.6.13 Machine Non-Maskable Interrupt Vector (mnmivec).......... 34 5.6.14 Machine Trap Handler Scratch Register (mscratch)......... 35 5.6.15 Machine Exception Program Counter Register (mepc)........ 35 5.6.16 Machine Trap Cause Register (mcause)................ 35 5.6.17 Machine Trap Value Register (mtval)................. 36 5.6.18 Counter-Enable Registers ([m|s]counteren)............. 37 5.6.19 Machine Cycle Counter (mcycle, mcycleh).............. 37 5.6.20 Machine Instructions-Retired counter (minstret, minstreth).... 37 5.6.21 Machine Performance counters (mhpmcounter, mhpmcounter).... 37 5.6.22 Machine Performance event selectors (mhpevent)........... 38 5.7 Supervisor Mode CSRs.............................. 38 5.7.1 Supervisor Status Register (sstatus).................. 38 5.7.2 Supervisor Trap Delegation Registers (sedeleg, sideleg)...... 38 5.7.3 Supervisor Interrupt Registers (sip, sie)................ 39 5.7.4 Supervisor Trap Vector Register (stvec)................ 40 5.7.5 Supervisor Scratch Register (sscratch)................ 41 5.7.6 Supervisor Exception Program Counter (sepc)............ 41 5.7.7 Supervisor Cause Register (scause).................. 41 5.7.8 Supervisor Trap Value Register (stval)................ 42 5.7.9 Counter-Enable Register (scounteren)................ 43 iii RV12 RISC-V CPU Core (v1.3) Roa Logic 5.8 User Mode CSRs................................. 43 5.8.1 User Trap Setup & Handling CSRs................... 43 5.8.2 Cycle counter for RDCYCLE instruction (cycle)........... 43 5.8.3 Time counter for RDTIME instruction (time)............. 43 5.8.4 Instruction-retire counter for RDINSTRET instruction (instret). 44 5.8.5 High Performance Monitoring Counters (hpmcounter)........ 44 5.8.6 Upper 32bits of cycle (cycleh - RV32I only)............. 44 5.8.7 Upper 32bits of instret (instreth - RV32I only)........... 44 5.8.8 Upper 32bits of hpmcounter (hpmcounterh - RV32I only)...... 44 5.9 Physical Memory Protection CSRs....................... 44 5.9.1 Address Matching............................ 45 5.9.2 Locking and Privilege Mode....................... 46 5.9.3 Priority and Matching Logic...................... 46 6 External Interfaces 48 6.1 AMBA3 AHB-Lite................................ 48 6.1.1 HRESETn................................. 48 6.1.2 HCLK................................... 48 6.1.3 IHSEL................................... 49 6.1.4 IHADDR................................. 49 6.1.5 IHRDATA................................. 49 6.1.6 IHWRITE................................. 49 6.1.7 IHSIZE.................................. 49 6.1.8 IHBURST................................. 49 6.1.9 IHPROT................................. 50 6.1.10 IHTRANS................................. 50 6.1.11 IHMASTLOCK.............................. 50 6.1.12 IHREADY................................ 50 6.1.13 IHRESP.................................. 50 6.1.14 DHSEL.................................. 50 6.1.15 DHADDR................................. 51 6.1.16 DHRDATA................................ 51 6.1.17 DHWDATA................................ 51 6.1.18 DHWRITE................................ 51 6.1.19 DHSIZE.................................. 51 6.1.20 DHBURST................................ 51 iv RV12 RISC-V CPU Core (v1.3) Roa Logic 6.1.21 DHPROT................................. 52 6.1.22 DHTRANS................................ 52 6.1.23 DHMASTLOCK............................. 52 6.1.24 DHREADY................................ 52 6.1.25 DHRESP................................. 52 6.2 Interrupts..................................... 53 6.2.1 EXT NMI................................. 53 6.2.2 EXT TINT................................ 53 6.2.3 EXT SINT................................ 53 6.2.4 EXT INT................................. 54 6.3 Physical Memory Protection........................... 54 6.3.1 pma cfg i................................. 55 6.3.2 pma adr i................................. 55 7 Debug Unit 57 7.1 Introduction.................................... 57 7.2 Debug Controller Interface............................ 57 7.2.1 dbg stall.................................. 57 7.2.2 dbg strb.................................. 57 7.2.3 dbg we................................... 58 7.2.4 dbg addr................................. 58 7.2.5 dbg dati.................................. 58 7.2.6 dbg dato................................. 58 7.2.7 dbg bp................................... 58 7.3 Register Map................................... 58 7.4 Internal Register Map.............................. 59 7.4.1 Debug Control Register DBG CTRL .................... 59 7.4.2 Debug Breakpoint Hit Register DBG HIT ................ 60 7.4.3 Debug Interrupt Enable Register DBG IE ................ 60 7.4.4 Debug Exception Cause Register DBG CAUSE .............. 61 7.4.5 Debug Breakpoint Control Registers DBG CTRLx ............ 62 7.4.6 Debug Breakpoint Data Registers DBG DATAx ............. 63 8 Resources 64 9 Acknowledgements 65 v RV12 RISC-V CPU Core (v1.3) Roa Logic