Introduction to Digital Design © V. Angelov VHDL-FPGA@PI 2013 1 Introduction to Digital Design • Why digital processing? • Basic logical circuits, first conclusions • Combinational circuits – Adder, multiplexer, decoder ... • Sequential circuits – Circuits with memory – State machine, synchronous circuits • General structure of a digital design – Top-down – Hardware/software © V. Angelov VHDL-FPGA@PI 2013 2 Why digital processing (1)? • The world is to a good approximation analogue • The result of some measurement can theoretically take continuous values, but we store it as a discrete value, multiple of some unit • In most of the measurements additional corrections and processing of the primary information are necessary d a2+ b 2 dt dt ∫ ∑ ∏ © . AngelovV HDL-FPGA@PI 2013 V 3 Why digital processing (2)? • Block diagram of some measurement device A Digital Analog D Proc. Noise, Discretization Rounding Disturbances, error, errors Nonlinearity, Nonlinearity Temperature, Supply voltage • How to arrange the full processing in order to get the best results? © V. Angelov VHDL-FPGA@PI 2013 4 Why digital processing (3)? • Where to do what? – the tendency is to start the digital processing as early as possible in the complete chain • How ? This is our main subject now 14 F P 1 IC G A V S CC A 14 13 12 11 10 9 8 CPU 1234567 GND © V. Angelov VHDL-FPGA@PI 2013 5 Notations of the logic elements • The most used are shown below • Frequent use of non-standard symbols A Y A A Y=(A*B) A Y Y B B B B AND OR NAND XNOR A Y A A Y A Y=(A+B) Y B B B B AND OR XOR NOR A B Y A B Y A B Y 0 0 0 0 0 0 0 0 0 Y = A 0 1 0 0 1 1 A 0 1 1 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 NOT 1 1 0 A & Y A 1 Y A 1 Y B B B © V. Angelov VHDL-FPGA@PI 2013 6 Useful Boolean relations A+!A = 1 A+ A = A A+ 0 = A A+ 1 = 1 A+B = B+A A*!A = 0 A+(B+C) = (A+B)+C A* A = A !(!A)= A A*(B+C) = A*B+A*C A* 0 = 0 A+(A*B) = A A* 1 = A AND * A+(!A*B) = A+B OR !(A+B) = !A * !B A*B = B*A XOR : :⋅ NOT ! + ~ ∨ ∧ A*(B*C) = (A*B)*C © . AngelovV + ⊕ A+(B*C) = (A+B)*(A+C)commutative (A*B)+(!A*C) = (A+C)*(!A+B)A*(A+B) = A associa iv A*(!A+B)= t e !(A*B) = !A + !B distributive A*B absorptive de Morgan's HDL-FPGA@PI 2013 V 7 NAND or NOR can do everything… with NAND with NOR NOT NAND NOR NOR AND NAND NAND NOR NOR NAND OR NAND NOR NOR NAND © V. Angelov VHDL-FPGA@PI 2013 8 XOR with NAND or NOR = = XOR A :+: B = A*!B + !A*B A + B = !(!A*!B) = OR (de Morgan) A:+:B = (A + B)*(!A + !B)= (A + B)*!(A * B) (de Morgan) © V. Angelov VHDL-FPGA@PI 2013 9 Simplifying Boolean expressions F=A*!C + A*!B + !A*B*!C + !A*!B = !C*(A+!A*B) + !B = !C*(A+B)+!B = = !C*A+!C*B+!B = A*!C + !B + !C = !B + !C A+(A*B) = A A+(!A*B)= A+B For A=0 Î F=B*!C +!B = !B+!C F=A*!C + A*!B + !A*B*!C + !A*!B For A=1 Î F=!C+!B For B=0 Î F=A*!C + A + !A = 1 F=A*!C + A*!B + !A*B*!C + !A*!B For B=1 Î F=A*!C + !A*!C = !C F(a1, a2, … aN) = F(0, a2, … aN) 0 F = a *F(1, a , … a ) + !a *F(0, a , … a ) 1 1 2 N 1 2 N F(1, a2, … aN) a1 With 4:1 mux, two variables can be eliminated © V. Angelov VHDL-FPGA@PI 2013 10 What kind of logical elements do we need? • Exactly like a house, that can be built using many identical small bricks, one logical circuit can be built using many identical NOR (OR- NOT) or NAND (AND-NOT) elements VCC • For practical reasons it is much better to have a rich set of different logical elements, this will save area and power and will speed up the circuit © V. Angelov VHDL-FPGA@PI 2013 11 Sum of products representation C B A • Truth table ABC Y 000 1 Y = !A*!B*!C + !A*B*C + A*!B*C + A*B*!C + A*B*C 001 0 010 0 011 1 Y 1 00 0 101 1 110 1 111 1 A A B B C C • If the function is more frequently 1, it is better to calculate the inverted function in order to have less terms: Y = ! ( !A*!B*C + !A*B*!C + A*!B*!C ) © V. Angelov VHDL-FPGA@PI 2013 12 Karnaugh Map (K-Map) with 3 signals B Y = !A*!B*!C+!A*B*C+A*!B*C+A*B*!C+A*B*C B B A 1 0 1 0 Y = !A*!B*!C + A*B + A*C + B*C A 0 1 1 1 C C B B B Y =!B*C+A*!B*!C+!A*!B*C+!A*B*C A 0 0 1 1 Y = A*!B + !A*C A 1 0 0 1 C C © V. Angelov VHDL-FPGA@PI 2013 13 K-Map with 4 signals D The four corner cells can D D be combined together as 1 0 0 1 !B*!D A 0 1 0 0 The two cells bottom left B can be combined as 1 0 0 0 A*!C*!D A 1 0 0 1 One minterm remains !B*!D !A*B*!C*D C C Finally we get: A*!C*!D F = !B*!D + A*!C*!D + !A*B*!C*D © V. Angelov VHDL-FPGA@PI 2013 14 K-Map with don't care D !A*!C D D If the function is not used in some combinations (x - don't 1 x 0 1 care) of the input signals, we A !A*B are free to replace any x with x 1 x x 0 or 1. B 1 0 x 0 In this example we have two A options to include the 1 0 0 1 !B*!D minterm !A*B*!C*D C C F = !B*!D + !C*!D + !A*!C !C*!D F = !B*!D + !C*!D + !A*B © V. Angelov VHDL-FPGA@PI 2013 15 K-Map for XOR D F = A :+: B :+: C :+: D D D 0 1 0 1 When going from one field to A any neighbour field in the K- 1 0 1 0 map, only ONE signal is B changed (Gray code, see later) 0 1 0 1 but the output toggles. A As can be seen, this prevents 1 0 1 0 any optimization, the function can be built by 8 product terms. C C In the general case of XOR between N signals, the number of product terms needed is 2N-1! Actually XOR is the worst function to be implemented as sum of products. © V. Angelov VHDL-FPGA@PI 2013 16 Conclusions(1) – PAL/CPLD/HDL • The sum of products representation was a good move! It seems to be a universal method (with some exceptions) to build any logical function – PAL and CPLD • Drawing of the circuit is tedious and not very reliable! • Writing of equations seems to be easier and more reliable → languages to describe hardware (HDL - hardware description language) © V. Angelov VHDL-FPGA@PI 2013 17 Conclusions(2) – ASIC Another possibility is to have many different logic functions. Here are shown only a small subset of the variations with AND-OR- NOT primitive functions available in a typical ASIC library AO21M20 AO21M10 AO32 AO211 AO22 AOI211 AO31M10 AO22M20 AOI22M10 AO22M10 AO31 All about 130 units + with different fanout capability © V. Angelov VHDL-FPGA@PI 2013 18 Conclusions(3) – LUT/FPGA • Another possible architecture for logical functions is to implement the truth table directly as a ROM • When increasing the number of the inputs N, the size of the memory grows very quickly as 2N! • If we have reprogrammable small memory blocks (LUT - Look Up Table), we could easily realize any function – the only limit is the number of the input signals a 0 0 0 : 1 0 0 1 : 0 The FPGAs contain a lot b 0 1 0 : 0 F(a, b, c) c 0 1 1 : 1 of LUT with 4 to 6 inputs + … LUT something more • For larger number of inputs we need to do something © V. Angelov VHDL-FPGA@PI 2013 19 Conclusions(4) – FPGA • Another possible architecture is to use multiplexers • Examples of simple 2-input logical functions built with 2:1 multiplexer '0' A Y 1 Y '1' = 0 A This approach is A '1' Y 1 Y used in some FPGA B B = 0 architectures A A B Y 1 Y B '0' = 0 A A B 1 Y B B = 0 A © V. Angelov VHDL-FPGA@PI 2013 20 Combinational circuits • ... are the circuits, where the outputs depend only on the present values of the inputs • Practically there is always some delay in the reaction of the circuit, depending on the temperature, supply voltage, the particular input and the state of the other inputs • it is good to know the min and max values (worst/best case) A1 F(A1, A2, ..