Master Thesis Computer Science Thesis no: MCS-2010-28 May 2010 Performance Tradeoffs in Software Transactional Memory Gulfam Abbas Naveed Asif SchoolSchool of Computing of Computing BlekingeBlekinge Institute Institute of Technology of Technology SwedenBox 520 SE – 372 25 Ronneby Sweden This thesis is submitted to the School of Computing at Blekinge Institute of Technology in partial fulfillment of the requirements for the degree of Master of Science in Computer Science. The thesis is equivalent to 20 weeks of full time studies. Contact Information: Author(s): Gulfam Abbas Address: Älgbacken 4:081, 372 34 Ronneby, Sweden. E-mail: [email protected] Naveed Asif Address: c/o Gulfam Abbas, Älgbacken 4:081, 372 34 Ronneby, Sweden . E-mail: [email protected] University advisor(s): Professor Dr. Håkan Grahn School of Computing Blekinge Institute of Technology, Sweden School of Computing Blekinge Institute of Technology Internet : www.bth.se/com SE – 371 79 Karlskrona Phone : +46 455 38 50 00 Sweden Fax : +46 455 38 50 53 ABSTRACT Transactional memory (TM), a new programming paradigm, is one of the latest approaches to write programs for next generation multicore and multiprocessor systems. TM is an alternative to lock-based programming. It is a promising solution to a hefty and mounting problem that programmers are facing in developing programs for Chip Multi-Processor (CMP) architectures by simplifying synchronization to shared data structures in a way that is scalable and compos-able. Software Transactional Memory (STM) a full software approach of TM systems can be defined as non-blocking synchronization mechanism where sequential objects are automatically converted into concurrent objects. In this thesis, we present performance comparison of four different STM implementations – RSTM of V. J. Marathe, et al., TL2 of D. Dice, et al., TinySTM of P. Felber, et al. and SwissTM of A. Dragojevic, et al. It helps us in deep understanding of potential tradeoffs involved. It further helps us in assessing, what are the design choices and configuration parameters that may provide better ways to build better and efficient STMs. In particular, suitability of an STM is analyzed against another STM. A literature study is carried out to sort out STM implementations for experimentation. An experiment is performed to measure performance tradeoffs between these STM implementations. The empirical evaluations done as part of this thesis conclude that SwissTM has significantly higher throughput than state-of-the-art STM implementations, namely RSTM, TL2, and TinySTM, as it outperforms consistently well while measuring execution time and aborts per commit parameters on STAMP benchmarks. The results taken in transaction retry rate measurements show that the performance of TL2 is better than RSTM, TinySTM and SwissTM. Keywords: Multiprocessor, Concurrent Programming, Synchronization, Software Transactional Memory, Performance I ACKNOWLEDGEMENTS In the Name of Allah who is The Most Merciful and Beneficent Prophet Mohammad (Peace Be Upon Him) said: “Seek knowledge from the cradle to the grave” We would like to congratulate and extend our gratitude for Professor Dr. Håkan Grahn on effectively guiding us in the achievement of this critical milestone. The successful completion of this research work was not likelihood without Professor Dr. Håkan Grahn consistent and valuable support. The unconditional love, prayers, and sacrifices that our parents always gifted us are worthwhile mentioning. It would not have been possible for us to achieve this big success without their pure support. In general we also would like to pay are special thanks to all our friends for their direct and indirect support which motivated us during all the times. At last but not least we dedicate our degree to the great nation of ISLAMIC REPUBLIC OF PAKISTAN, the land which gave us identity, prestige, honor and the will to learn. II CONTENTS ABSTRACT ............................................................................................................................ I ACKNOWLEDGEMENTS .................................................................................................. II CONTENTS ......................................................................................................................... III LIST OF ACRONYMS ......................................................................................................... V LIST OF FIGURES ............................................................................................................. VI LIST OF TABLES .............................................................................................................. VII INTRODUCTION .................................................................................................................. 1 THESIS OUTLINE ................................................................................................................................. 2 1 CHAPTER 1: PROBLEM DEFINITION .................................................................... 3 1.1 PROBLEM FOCUS .................................................................................................................... 3 1.2 AIMS AND OBJECTIVES ........................................................................................................... 3 1.3 RESEARCH QUESTIONS .......................................................................................................... 4 2 CHAPTER 2: BACKGROUND .................................................................................... 5 2.1 SINGLE CHIP PARALLEL COMPUTERS .................................................................................... 5 2.2 DATABASE SYSTEMS AND TRANSACTIONS ............................................................................ 5 2.3 TRANSACTIONS VS. LOCKS .................................................................................................... 6 2.4 TRANSACTIONAL MEMORY .................................................................................................... 7 2.4.1 Hardware Transactional Memory .................................................................................... 8 2.4.2 Software Transactional Memory ....................................................................................... 8 2.4.3 Hybrid Transactional Memory ......................................................................................... 9 2.5 STM DESIGN ALTERNATIVES .............................................................................................. 10 2.5.1 Transaction Granularity ................................................................................................. 10 2.5.2 Update Policy ................................................................................................................. 10 2.5.3 Write Policy .................................................................................................................... 10 2.5.4 Acquire Policy ................................................................................................................ 11 2.5.5 Read Policy ..................................................................................................................... 11 2.5.6 Conflict Detection ........................................................................................................... 11 2.5.7 Concurrency Control ...................................................................................................... 11 2.5.8 Memory Management ..................................................................................................... 12 2.5.9 Contention Management ................................................................................................. 12 3 CHAPTER 3: METHODOLOGY .............................................................................. 14 3.1 QUALITATIVE RESEARCH METHODOLOGY .......................................................................... 14 3.1.1 Literature Review ............................................................................................................ 14 3.1.2 Background Study ........................................................................................................... 14 3.1.3 Selection and Suitability of STM systems ........................................................................ 14 3.1.4 Selection and Suitability of Benchmarks ......................................................................... 15 3.2 QUANTITATIVE RESEARCH METHODOLOGY ........................................................................ 15 3.2.1 Selection and Suitability of STM Performance Metrics .................................................. 15 3.2.2 Experimentation .............................................................................................................. 16 3.2.3 Analysis of Gathered Results .......................................................................................... 16 4 CHAPTER 4: THEORETICAL WORK .................................................................... 17 4.1 RSTM .................................................................................................................................. 17 4.1.1 RSTM Overview .............................................................................................................. 17 4.1.2 Design Features .............................................................................................................. 17 4.1.3 Implementation