Nios II Processor Reference Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com NII5V1-9.0 Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap- plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Contents Chapter Revision Dates . ix List of Figures . xi List of Tables . xiii Section I. Nios II Processor Design Chapter 1. Introduction Introduction . 1–1 Nios II Processor System Basics . 1–1 Getting Started with the Nios II Processor . 1–2 Customizing Nios II Processor Designs . 1–3 Configurable Soft-Core Processor Concepts . 1–4 Configurable Soft-Core Processor . 1–4 Flexible Peripheral Set and Address Map . 1–4 Standard Peripherals . 1–4 Custom Peripherals . 1–5 Custom Instructions . 1–5 Automated System Generation . 1–5 OpenCore Plus Evaluation . 1–5 Referenced Documents . 1–6 Document Revision History . 1–6 Chapter 2. Processor Architecture Introduction . 2–1 Processor Implementation . 2–3 Register File . 2–3 Arithmetic Logic Unit . 2–3 Unimplemented Instructions . 2–4 Custom Instructions . 2–4 Floating-Point Instructions . 2–4 Software Development Considerations . 2–6 Reset and Debug Signals . 2–7 Exception and Interrupt Controller . 2–7 Exception Controller . 2–7 Integral Interrupt Controller . 2–8 Interrupt Vector Custom Instruction . 2–8 Memory and I/O Organization . 2–9 Instruction and Data Buses . 2–10 Memory and Peripheral Access . 2–11 Instruction Master Port . 2–11 Data Master Port . 2–11 Shared Memory for Instructions and Data . 2–12 Cache Memory . 2–12 Configurable Cache Memory Options . 2–12 Effective Use of Cache Memory . 2–12 Cache Bypass Methods . 2–13 © March 2009 Altera Corporation Nios II Processor Reference Handbook Preliminary iv Contents Tightly-Coupled Memory . 2–13 Accessing Tightly-Coupled Memory . 2–14 Effective Use of Tightly-Coupled Memory . 2–14 Address Map . 2–14 Memory Management Unit . 2–14 Memory Protection Unit . 2–15 JTAG Debug Module . 2–16 JTAG Target Connection . 2–17 Download and Execute Software . 2–17 Software Breakpoints . 2–17 Hardware Breakpoints . 2–17 Hardware Triggers . ..