UltraSPARC® IIIi Processor User’s Manual Version 1.0 June 2003 Copyright © 2003 Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, California 95054, U.S.A. All rights reserved. Sun, Sun Microsystems, the Sun logo, Java, Solaris, Chorus, VIS, OpenBootPROM, UltraSPARC IIIi Processor User’s Manual and SPARC are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. Use of any spare or replacement processors is limited to repair or one-for-one replacement of processors in products exported in compliance with U.S. export laws. Use of processors as product upgrades unless authorized by the U.S. Government is strictly prohibited. DOCUMENTATION IS PROVIDED "AS IS" AND ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD TO BE LEGALLY INVALID. Table of Contents Preface xxv Acronyms and Definitions xxxi Section I: Processor Introduction 1. Introducing the UltraSPARC IIIi Processor ....................................................................3 1.1 Overview ................................................................................................................3 1.2 Features ..................................................................................................................4 1.3 Summary ................................................................................................................5 2. UltraSPARC IIIi Processor in a System ...........................................................................9 2.1 System Configurations ...........................................................................................9 2.1.1 Four-Processor System .............................................................................9 2.1.2 Two-Processor System .............................................................................11 2.1.3 One-Processor System ..............................................................................12 2.2 JBUS Interface .......................................................................................................13 2.3 Memory System .....................................................................................................13 2.4 Power Management ................................................................................................14 Table of Contents i Section II: Architecture and Functions 3. UltraSPARC IIIi Processor Architecture Basics ............................................................. 17 3.1 Component Overview ............................................................................................ 17 3.1.1 Instruction Fetch and Buffering ............................................................... 19 3.1.2 Execution Pipelines ................................................................................. 20 3.1.3 Load/Store Unit ....................................................................................... 20 3.1.4 Memory Management Units .................................................................... 22 3.1.5 Embedded Cache Unit (Level-2 Unified Cache) ...................................... 23 3.1.6 JBUS Interface Unit ................................................................................. 23 3.1.7 Memory Controller Unit .......................................................................... 23 3.2 Processor Operating Modes ................................................................................... 24 3.2.1 Privileged Mode ....................................................................................... 24 3.2.2 Non-Privileged Mode ............................................................................... 24 3.2.3 Reset and RED_State ............................................................................... 24 3.2.4 Error Handling ......................................................................................... 27 3.2.5 Debug and Diagnostics Mode .................................................................. 29 4. Instruction Execution ........................................................................................................31 4.1 Introduction ........................................................................................................... 31 4.1.1 NOP, Neutralized, and Helper Instructions .............................................. 31 4.2 Processor Pipeline ................................................................................................. 32 4.2.1 Instruction Dependencies ......................................................................... 35 4.2.2 Instruction-Fetch Stages .......................................................................... 36 4.2.3 Instruction Issue and Queue Stages ......................................................... 37 4.2.4 Execution Pipeline ................................................................................... 38 4.2.5 Trap and Done Stages .............................................................................. 40 4.3 Pipeline Recirculation ............................................................................................ 41 4.4 Grouping Rules ...................................................................................................... 41 4.4.1 Execution Order ....................................................................................... 42 ii UltraSPARC IIIi Processor User’s Manual • June 2003 4.4.2 Integer Register Dependencies to Instructions in the MS Pipeline ...........42 4.4.3 Integer Instructions Within a Group .........................................................43 4.4.4 Same-Group Bypass .................................................................................44 4.4.5 Floating-Point Unit Operand Dependencies .............................................44 4.4.6 Grouping Rules for Register-Window Management Instructions .............46 4.4.7 Grouping Rules for Reads and Writes of the ASRs ..................................46 4.4.8 Grouping Rules for Other Instructions .....................................................47 4.5 Conditional Moves .................................................................................................48 4.6 Instruction Latencies and Dispatching Properties ..................................................49 4.6.1 Latency .....................................................................................................49 4.6.2 Blocking ...................................................................................................50 4.6.3 Pipeline ....................................................................................................50 4.6.4 Break and SIG ..........................................................................................50 Section III: Execution Environment 5. Data Formats ......................................................................................................................59 5.1 Integer Data Formats ..............................................................................................60 5.1.1 Integer Data Value Range .........................................................................60 5.1.2 Integer Data Alignment ............................................................................61 5.1.3 Signed Integer Data Types ........................................................................61 5.1.4 Unsigned Integer Data Types ...................................................................63 5.1.5 Tagged Word ............................................................................................64 5.2 Floating-Point Data Formats ..................................................................................65 5.2.1 Floating-Point Data Value Range .............................................................65 5.2.2 Floating-Point Data Alignment ................................................................65 5.2.3 Floating-Point, Single-Precision ..............................................................66 5.2.4 Floating-Point, Double-Precision .............................................................67 5.2.5 Floating-Point, Quad-Precision ................................................................68 Table of Contents iii 5.3 VIS Execution Unit Data Formats ......................................................................... 69 5.3.1 Pixel Data Format .................................................................................... 70 5.3.2 Fixed-Point Data Formats ........................................................................ 70 6. Registers ............................................................................................................................. 73 6.1 Introduction ........................................................................................................... 73 6.1.1 Document Notes ...................................................................................... 74 6.2 Integer Unit General-Purpose r Registers .............................................................. 74 6.2.1 Windowed (in/local/out) r Registers ........................................................ 76 6.2.2 Global r Register Sets .............................................................................. 76 6.3 Register Window Management .............................................................................