University of Central Florida STARS Electronic Theses and Dissertations, 2004-2019 2011 High Linearity 5.8 Ghz Power Amplifier With An Internal Linearizer Yiheng Wang University of Central Florida Part of the Electrical and Electronics Commons Find similar works at: https://stars.library.ucf.edu/etd University of Central Florida Libraries http://library.ucf.edu This Masters Thesis (Open Access) is brought to you for free and open access by STARS. It has been accepted for inclusion in Electronic Theses and Dissertations, 2004-2019 by an authorized administrator of STARS. For more information, please contact [email protected]. STARS Citation Wang, Yiheng, "High Linearity 5.8 Ghz Power Amplifier With An Internal Linearizer" (2011). Electronic Theses and Dissertations, 2004-2019. 1988. https://stars.library.ucf.edu/etd/1988 High Linearity 5.8 GHz Power Amplifier with an Internal Linearizer by YIHENG WANG M.S. Beihang University, 2009 A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in the Department of Electrical Engineering and Computer Science in the College of Engineering and Computer Science at the University of Central Florida Orlando, Florida Spring Term 2011 Major Professor: Jiann.S.Yuan © 2011 YihengWang ii ABSTRACT A 5.8 GHz RF Power Amplifier (PA) is designed and fabricated in this work, which has very high linearity through a built-in linearizer. The PA is designed, post-layout simulated by Agilent Advanced Design System (ADS) software and fabricated by Win-Semiconductors 0.15µm pHEMT process technology. The post-layout simulation results illustrate the power amplifier can obtained an output power of 23.98 dBm, a power gain of 32.28 dB and a power added efficiency (PAE) of 29% at saturation region, the 3rd intermodulation distortion (IMD3) of -37.7 dBc at 0 dBm input power is attained when operation frequency is 5.8 GHz. We finally obtain that the output power of 17.97 dBm and power gain of 27.97 dB at input power of -10 dBm, PAE of 11.65% at input power of 0 dBm and the IMD3 of -25.66 dBc at -20 dBm input power by measurement, when operation frequency is 5.2 GHz. So the overall RF performance of the PA demonstrates high power, high efficiency and high linearity. iii ACKNOWLEDGMENTS I would like to express my gratitude to my advisor, Professor Jiann S. Yuan, for his warm, sincere, and approachable support, patience, and encouragement throughout my graduate studies. He contributed many critical directions and suggestions to this work while offering freedom to pursue and manage my own research. His technical and editorial advice was essential to the completion of this thesis and has taught me innumerable insights on the workings of academic research in general. The knowledge and the philosophy that he taught me will be the guide for my professional life. My thanks also go to the members of my thesis committee, Dr. Kalpathy B. Sundaram and Dr. Xun Gong for reading previous drafts of this thesis and providing many valuable comments that improved the presentation and contents of this thesis. In particular, Dr. Xun Gong and his PHD student Mr. Xinhua Ren provided a lot of help to me, when I did the on-wafer chip measurement. I am grateful to all my colleagues in the lab - Dr. Yidong Liu, Ms. Shuyu Chen, Ms. Yuying Zhang, Ms. Hongxia Tang, Mr. Karan S Kutty, Mr. Chengcheng Xiao, Mr.Giji Skaria, Mr. Jason Steighner. Especially, I discussed lots of issues with Shuyu and Karan about the analysis, design, implementation, and optimization of RF circuit. We have collaborated in many issues, and I have learned many things from them. Last, but not least, I would like to thank my wife Xinxin for her understanding and love during the past few years. Her support and encouragement was in the end what made this thesis iv possible. My parents - Dawei and Zhimin, parent-in-law – Jian and Xiaoping, receive my deepest gratitude and love for their dedication and many years of support during my studies. v TABLE OF CONTENTS LIST OF FIGURES ..................................................................................................................... viii LIST OF TABLES ......................................................................................................................... xi LIST OF ACRONYMS/ABBREVIATIONS ............................................................................... xii CHAPTER ONE: INTRODUCTION ............................................................................................. 1 CHAPTER TWO: CIRCUIT DESIGN .......................................................................................... 5 Power Amplifier Design ............................................................................................................. 5 Load Pull and Source Pull Simulation .................................................................................... 7 Matching Network Design .................................................................................................... 10 Linearizer Design ...................................................................................................................... 12 Final Circuit .............................................................................................................................. 15 Pre-Layout Simulation .............................................................................................................. 17 CHAPTER THREE: LAYOUT AND POST-LAYOUT SIMULATION .................................... 21 Layout Design ........................................................................................................................... 21 Layout Analysis Result ............................................................................................................. 24 Post Layout Simulation ............................................................................................................. 26 CHAPTER FOUR: MEASUREMENT ........................................................................................ 39 Measurement Environment Seting Up ...................................................................................... 39 vi Measurement Instrument ...................................................................................................... 39 Chip Connection ................................................................................................................... 40 Measurement Environment ................................................................................................... 41 Measurement Results ................................................................................................................ 45 S-Parameter Measurement Results ....................................................................................... 45 Power Performance Measurement Result ............................................................................. 48 Result Discussion .................................................................................................................. 57 CHAPTER FIVE: CONCLUSION............................................................................................... 59 CHAPTER SIX: FUTURE WORK .............................................................................................. 60 LIST OF REFERENCES .............................................................................................................. 62 vii LIST OF FIGURES Figure 1: Block Diagram of Conventional Wireless Transceiver ................................................... 2 Figure 2: Two Stages PA Basic Architecture ................................................................................. 7 Figure 3: Load Pull Simulation Result............................................................................................ 9 Figure 4: Source Pull Simulation Result ....................................................................................... 10 Figure 5: Power Amplifier Circuit Diagram ................................................................................. 11 Figure 6: Principle of Gain Compensation ................................................................................... 13 Figure 7: Equivalent Circuit of Linearizer .................................................................................... 14 Figure 8: Linearizer Circuit Diagram ........................................................................................... 15 Figure 9: Final Circuit of High Linearity Power Amplifier .......................................................... 16 Figure 10: S Parameter Results of Pre-Layout Simulation ........................................................... 17 Figure 11: Stability Result of Pre-Layout Simulation .................................................................. 18 Figure 12: Power Performances of Pre-Layout Simulation .......................................................... 19 Figure 13: Linearity Result (IP3) of Pre-Layout Simulation ........................................................ 19 Figure 14: Linearity Comparison With Linearizer to Without Linearizer .................................... 20 Figure 15: Final Layout of Power Amplifier With Linearizer ...................................................... 23 Figure 16: Air Bridge Rule Check Result (Total Error Found: 0) ................................................ 24 Figure 17: Basic Rule Check Result (Total Error Found: 0) ........................................................ 25 Figure