EE 280 Introduction to Digital Logic Design Lecture 19. Multiplexers EE280 Lecture 19 19 - 1 Integrated Circuits Types IC can be classified into: – small-scale integration (SSI) NAND, MOR, AND, OR gates, inverters, flip-flops SSI package usually contains 1-4 gates, 6 inverters, and 1-2 flip-flops – medium-scale integration (MSI) adders, multiplexers, decoders, registers, counters, etc. MSI package usually contains equivalent of 12-100 gates – large-scale integration (LSI) memories, microprocessors, etc. LSI package usually contains equivalent of 100-few thousand gates – very large-scale integration (VLSI) memories, microprocessors, etc. VLSI package usually contains equivalent of several thousand gates or more EE280 Lecture 19 19 - 2 1 Multiplexers - Process of switching data from several channels into 1 channel is called multiplexing or data selecting. - A MUX is essentially a switch. e.g.: Computer with 4 information sources: Data sources Channels TPR-1 Computer 1 MUX TPR-2 2 Digital 3 Output CRT 4 S 0 S 1 Analog Temp. ADC Address sensor inputs EE280 Lecture 19 19 - 3 2-to-1 Multiplexer If A = 0 then Z = I0 I0 2 to 1 If A = 1 then Z = I1 Z MUX I1 0, 1 A (Control) EE280 Lecture 19 19 - 4 2 4-to-1 Multiplexer ABZ I0 I1 4 to 1 Z I2 MUX I3 A B Z = A’ B’ I0 + A’ B I1 + A B’ I2 + A B I3 EE280 Lecture 19 19 - 5 Internal Schematics of a 4-to-1 Multiplexer I0 I1 Data Data inputs output I2 I3 Z = A’ B’ I0 + A’ B I1 + A B’ I2 + A B I3 A B Select inputs EE280 Lecture 19 19 - 6 3 Internal Schematics of a 4-to-1 Multiplexer I0 Data I1 Data inputs output I2 I3 Select inputs determine the position of the switch Equivalent switch EE280 Lecture 19 19 - 7 The Multiplexer/Data Selector 8-to-1 MUX requires control lines 2n-to-1 MUX requires control lines In general, for a MUX with n control I/P's and data inputs: Z = where mi = ith minterm of the control variables Ii = input data on the ith I/P line 1 or more MUX's in an IC package EE280 Lecture 19 19 - 8 4 The Multiplexer/Data Selector x 0 2 to 1 Z y MUX 0 0 2-to-1 quad MUX 4 MUX per DIP 0,1 4-to-1 dual MUX 2 MUX per DIP x 1 2 to 1 8-to-1 dual MUX 2 MUX per DIP Z1 y1 MUX 16-to-1 dual MUX 2 MUX per DIP 0,1 x 2 2 to 1 Z2 y2 MUX 0,1 x 3 2 to 1 Z3 y3 MUX 0,1 EE280 Lecture 19 19 - 9 A (2-to-1 quad MUX control) 5.