DEGREE PROJECT IN TECHNOLOGY, FIRST CYCLE, 15 CREDITS STOCKHOLM, SWEDEN 2018 Dynamic Allocation for Embedded Heterogeneous Memory An Empirical Study THOMAS PETERSON KTH ROYAL INSTITUTE OF TECHNOLOGY SCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Abstract Embedded systems are omnipresent and contribute to our lives in many ways by instantiating functionality in larger systems. To operate, embedded systems require well-functioning software, hardware as well as an interface in-between these. The hardware and software of these systems is under constant change as new technologies arise. An actual change these systems are undergoing are the experimenting with different memory management techniques for RAM as novel non-volatile RAM(NVRAM) technologies have been invented. These NVRAM technologies often come with asymmetrical read and write latencies and thus motivate designing memory consisting of multiple NVRAMs. As a consequence of these properties and memory designs there is a need for memory management that minimizes latencies. This thesis addresses the problem of memory allocation on heterogeneous memory by conducting an empirical study. The first part of the study examines free list, bitmap and buddy system based allocation techniques. The free list allocation technique is then concluded to be superior. Thereafter, multi-bank memory architectures are designed and memory bank selection strategies are established. These strategies are based on size thresholds as well as memory bank occupancies. The evaluation of these strategies did not result in any major conclusions but showed that some strategies were more appropriate for some application behaviors. Keywords Memory management, NVRAM, Scratchpad memory, Embedded systems KTH ROYAL INSTITUTE OF TECHNOLOGY INFORMATION AND COMMUNICATION TECHNOLOGY Abstract Inbyggda system existerar allestädes och bidrar till våran livsstandard på flertalet avseenden genom att skapa funktionalitet i större system. För att vara verksamma kräver inbyggda system en välfungerande hård- och mjukvara samt gränssnitt mellan dessa. Dessa tre måste ständigt omarbetas i takt med utvecklingen av nya användbara teknologier för inbyggda system. En förändring dessa system genomgår i nuläget är experimentering med nya minneshanteringstekniker för RAM-minnen då nya icke-flyktiga RAM-minnen utvecklats. Dessa minnen uppvisar ofta asymmetriska läs och skriv fördröjningar vilket motiverar en minnesdesign baserad på flera olika icke- flyktiga RAM. Som en konsekvens av dessa egenskaper och minnesdesigner finns ett behov av att hitta minnesallokeringstekniker som minimerar de fördröjningar som skapas. Detta dokument adresserar problemet med minnesallokering på heterogena minnen genom en empirisk studie. I den första delen av studien studerades allokeringstekniker baserade på en länkad lista, bitmapp och ett kompissystem. Med detta som grund drogs slutsatsen att den länkade listan var överlägsen alternativen. Därefter utarbetades minnesarkitekturer med flera minnesbanker samtidigt som framtagandet av flera strategier för val av minnesbank utfördes. Dessa strategier baserades på storleksbaserade tröskelvärden och nyttjandegrad hos olika minnesbanker. Utvärderingen av dessa strategier resulterade ej i några större slutsatser men visade att olika strategier var olika lämpade för olika beteenden hos applikationer. Nyckelord Minneshantering, NVRAM, Scratchpad minne, Inbyggda system Acknowledgement I would like to thank Guillaume Salagnac, my supervisor at INSA-Lyon, for his invaluable feedback and guiding throughout the research and writing of this report. I would also like to thank Tristan Delizy for providing and continuously maintaining the simulator. Finally, I would like to thank my family and my girlfriend for supporting me throughout my studies and the research conducted in this thesis. Thank you! Stockholm, January 2018 Thomas Peterson Table of Contents List of Tables ...................................................................................................................... i List of Figures ................................................................................................................... ii Abbreviations ................................................................................................................. iii Glossary ............................................................................................................................. iv 1 Introduction ............................................................................................................. 1 1.1 Background .................................................................................................................. 1 1.1.1 Evaderis and Dycton ............................................................................................................................. 1 1.1.2 Problem Background ............................................................................................................................ 2 1.2 Problem Statement .................................................................................................. 3 1.3 Purpose ........................................................................................................................... 3 1.4 Goal ................................................................................................................................... 3 1.5 Methodology ................................................................................................................ 4 1.6 Delimitations ............................................................................................................... 4 1.7 Outline ............................................................................................................................. 5 2 Background ............................................................................................................... 6 2.1 A Note on Embedded Systems ........................................................................... 6 2.2 A Multitude of NVRAMs ........................................................................................ 6 2.2.1 Charge storage .......................................................................................................................................... 7 2.2.2 Resistance Switching ............................................................................................................................ 8 2.3 Checkpointing in Embedded Systems ........................................................... 9 2.4 Memory Management ............................................................................................ 9 2.5 Dynamic Memory Allocators ............................................................................ 11 2.5.1 Free List Allocator ............................................................................................................................... 12 2.5.2 Bitmap Allocator .................................................................................................................................. 12 2.5.3 Buddy Allocator .................................................................................................................................... 13 2.6 Profiling Techniques for Evaluating Allocators .................................... 14 2.7 Typical Allocation Patterns Found in Programs .................................. 15 2.8 SystemC ........................................................................................................................ 16 3 Methodologies ...................................................................................................... 18 3.1 Approach ...................................................................................................................... 18 3.2 Phases ............................................................................................................................ 18 3.3 Evaluation criteria .................................................................................................. 19 3.3.1 Execution Time Evaluation ............................................................................................................ 19 3.3.2 Memory Usage Evaluation .............................................................................................................. 20 3.4 Implementation of the Allocators ................................................................. 21 3.5 Synthetic Profiling .................................................................................................. 22 3.6 Studying Real Program Behavior .................................................................. 23 3.7 Managing Multiple Banks Using a Memory Manager ....................... 23 3.7.1 Emulating NVRAM Using Memory Architectures ............................................................ 24 3.7.2 Applying Various Placement Strategies ................................................................................... 25 4 Results ....................................................................................................................... 26 4.1 Single-Bank Allocation Using Various Allocators ............................... 26 4.1.1 One Large Object – A Plateau ....................................................................................................... 27 4.1.2 Increasing the Memory – A Ramp .............................................................................................. 28