HDL Synthesis Guide Release 4.2 Copyright Copyright © 1991-1998 Exemplar Logic, Inc. All Rights Reserved Trademarks Exemplar Logic® and its Logo are registered trademarks of Exemplar Logic, Inc.; Galileo™, Galileo Extreme™, Leonardo™, Galileo FS™ and MODGEN™ are trademarks of Exemplar Logic, Inc.; Extreme Technology, FAST Synthesis and Synthesizing the next Millennium are servicemarks of Exemplar Logic, Inc. V-System/VHDL™ and V-System/Verilog™ are trademarks of Model Technology, Inc. Verilog® and Verilog-XL® are registered trademarks of Cadence Design Systems, Inc. All other trademarks remain the property of their respective owners. Disclaimer Although Exemplar Logic, Inc. has tested the software and reviewed the documentation, Exemplar Logic, Inc. makes no warranty or representation, either express or implied, with respect to this software and documentation, its quality, performance, merchantability, or fitness for a particular purpose. Exemplar Logic, Inc. 6503 Dumbarton Circle Fremont, CA 94555 Telephone: 800-632-3742 email: [email protected] Part No. 31315-R Contents 1. Introduction to VHDL Synthesis . 1-1 Overview. 1-1 VHDL and Synthesis. 1-2 In This Manual . 1-3 Customer Support . 1-4 2. VHDL Language Features . 2-1 Entities and Architectures . 2-1 Configuration . 2-3 Processes. 2-5 Literals . 2-8 Types . 2-9 Enumeration Types . 2-10 Syntax and Semantics . 2-10 Synthesis Issues. 2-11 Integer Types. 2-17 iii Syntax and Semantics . 2-17 Synthesis issues . 2-18 Floating-point Types . 2-19 Syntax and Semantics . 2-19 Synthesis Issues. 2-19 Physical Types . 2-20 Syntax and Semantics . 2-20 Synthesis Issues. 2-21 Array Types. 2-21 Syntax and Semantics . 2-21 Synthesis Issues. 2-23 Record Types . 2-24 Syntax and Semantics . 2-24 Synthesis Issues. 2-25 Subtypes . 2-25 Type Conversions . 2-27 IEEE 1076 Predefined Types . 2-28 IEEE 1164 Predefined Types . 2-28 Objects . 2-30 Signals. 2-30 Constants . 2-30 Variables . 2-31 Ports . 2-31 Generics . 2-32 iv HDL Synthesis Guide Loop Variables . 2-32 Statements . 2-33 Conditional Statements . 2-33 Selection Statements . 2-34 Loop Statements and Generate Statements . 2-35 Assignment Statements . 2-38 Operators. 2-40 IEEE 1076 Predefined Operators . 2-40 IEEE 1164 Predefined Operators . 2-43 Operator Overloading . 2-43 Attributes. 2-44 VHDL Predefined Attributes . 2-45 Exemplar Predefined Attributes . 2-45 User-Defined Attributes . 2-46 Usage Of Attributes . 2-46 Blocks . 2-48 Functions And Procedures. 2-49 Resolution Functions. 2-52 Syntax and Semantics . 2-52 Synthesis Issues . 2-53 BUS and REGISTER . 2-55 Component Instantiation . 2-58 Packages . 2-64 Aliases. 2-65 Contents v 3. The Art Of VHDL Synthesis. 3-1 Registers, Latches and Resets . 3-1 Level-Sensitive Latch . 3-2 Edge-Sensitive Flip-Flops. 3-3 The Event Attribute . 3-3 Synchronous Sets And Resets . 3-4 Asynchronous Sets And Resets . 3-5 Clock Enable . 3-7 Wait Statements . 3-8 Variables . 3-9 Predefined Flip-flops and Latches. 3-10 Assigning I/O Buffers From VHDL . 3-10 Automatic Assignment Using Chip Mode. 3-11 Manual Assignment Using The BUFFER_SIG Property . 3-11 Buffer Assignment Using Component Instantiation . 3-13 Three-state Buffers . 3-14 Bidirectional Buffers . 3-17 Busses . 3-18 State Machines . 3-18 General State Machine Description. 3-18 VHDL Coding Style For State Machines . 3-20 Power-up And Reset . 3-22 State Encoding . 3-22 Arithmetic And Relational Logic . 3-22 vi HDL Synthesis Guide Module Generation . 3-25 Resource Sharing . 3-25 Ranged Integers . 3-27 Advanced Design Optimization . 3-28 Technology-Specific Macros. 3-29 Multiplexers and Selectors . ..