REAL TIME 3-D GRAPHICS PROCESSING HARDWARE DESIGN USING FIELD- PROGRAMMABLE GATE ARRAYS. by James Ryan Warner B. S. in Computer Engineering, Pennsylvania State University, 1999 Submitted to the Graduate Faculty of Swanson School of Engineering in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering University of Pittsburgh 2008 i UNIVERSITY OF PITTSBURGH SWANSON SCHOOL OF ENGINEERING This thesis was presented by James Ryan Warner It was defended on September 18, 2008 and approved by Dr. Alexander Jones, Assistant Professor, Department of Electrical and Computer Engineering Dr. Allen Cheng, Assistant Professor, Department of Electrical and Computer Engineering Thesis Advisor: Dr. James T. Cain, Professor Emeritus, Department of Electrical and Computer Engineering ii Copyright © by James Ryan Warner 2008 iii REAL TIME 3-D GRAPHICS PROCESSING HARDWARE DESIGN USING FIELD- PROGRAMMABLE GATE ARRAYS James Ryan Warner, M.S. University of Pittsburgh, 2008 Three dimensional graphics processing requires many complex algebraic and matrix based operations to be performed in real-time. In early stages of graphics processing, such tasks were delegated to a Central Processing Unit (CPU). Over time as more complex graphics rendering was demanded, CPU solutions became inadequate. To meet this demand, custom hardware solutions that take advantage of pipelining and massive parallelism become more preferable to CPU software based solutions. This fact has lead to the many custom hardware solutions that are available today. Since real time graphics processing requires extreme high performance, hardware solutions using Application Specific Integrated Circuits (ASICs) are the standard within the industry. While ASICs are a more than adequate solution for implementing high performance custom hardware, the design, implementation and testing of ASIC based designs are becoming cost prohibitive due to the massive up front verification effort needed as well as the cost of fixing design defects. Field Programmable Gate Arrays (FPGAs) provide an alternative to the ASIC design flow. More importantly, in recent years FPGA technology have begun to improve in performance to the point where ASIC and FPGA performance has become comparable. In addition, FPGAs address many of the issues of the ASIC design flow. The ability to reconfigure FPGAs reduces the upfront verification effort and allows design defects to be fixed easily. iv This thesis demonstrates that a 3-D graphics processor implementation on and FPGA is feasible by implementing both a two dimensional and three dimensional graphics processor prototype. By using a Xilinx Virtex 5 ML506 FPGA development kit a fully functional wireframe graphics rendering engine is implemented using VHDL and Xilinx’s development tools. A VHDL testbench was designed to verify that the graphics engine works functionally. This is followed by synthesizing the design and real hardware and developing test applications to verify functionality and performance of the design. This thesis provides the ground work for push forward the use of FPGA technology in graphics processing applications. v TABLE OF CONTENTS PREFACE ................................................................................................................................. XIX 1.0 INTRODUCTION ........................................................................................................ 1 1.1 OVERVIEW ......................................................................................................... 1 1.2 STATEMENT OF THE PROBLEM ................................................................. 7 1.3 OUTLINE ............................................................................................................. 9 2.0 COMPUTER GRAHPICS RENDERING ............................................................... 10 2.1 MATHMATICS OVERVIEW ......................................................................... 12 2.1.1 Homogenous vectors ...................................................................................... 12 2.1.2 Coordinate System ......................................................................................... 13 2.1.3 Object Representation ................................................................................... 15 2.1.4 Affine Geometric Transformations .............................................................. 16 2.1.4.1 Translation Transformation .............................................................. 17 2.1.4.2 Scaling Transformation ...................................................................... 18 2.1.4.3 Rotation Transformation ................................................................... 20 2.1.4.4 Transformation Compositions ........................................................... 22 2.2 THE GRAPHICS PIPELINE ........................................................................... 26 2.2.1 Object Definition............................................................................................ 27 2.2.2 Scene Composition using World Coordinate Transformation .................. 28 vi 2.2.3 View Coordinates and the View Transformation ....................................... 29 2.2.4 3D Projections and the Clipping Transformation ...................................... 34 2.2.4.1 Perspective Projection ........................................................................ 37 2.2.4.2 Parallel Projection ............................................................................... 39 2.2.5 Clipping .......................................................................................................... 41 2.2.5.1 Cohen-Sutherland Two Dimensional Clipping ................................ 41 2.2.5.2 Cohen-Sutherland Three Dimensional Clipping .............................. 45 2.2.6 Screen Coordinate Transformation ............................................................. 49 2.2.7 Rasterization .................................................................................................. 51 3.0 THE GRAPHICS PROCESSING UNIT ................................................................. 56 3.1 GRAPHICS PIPELINE .................................................................................... 61 3.1.1 Matrix Multiplier Accelerator ...................................................................... 64 3.1.2 Clipping Design .............................................................................................. 67 3.1.3 Line Rasterization.......................................................................................... 79 3.1.4 Frame Buffer and Display Interface ............................................................ 83 3.2 CENTRAL PROCESSING UNIT .................................................................... 87 3.2.1 Graphics Pipeline Control Registers............................................................ 89 3.2.2 Other Peripherals .......................................................................................... 90 4.0 GRAPHIC PROCESSING UNIT IMPLEMENTATION AND TESTING ......... 91 4.1 HARDWARE DEVELOPMENT PLATFORM ............................................. 91 4.2 GRAPHICS PROCESSING UNIT IMPLEMENTATION ........................... 94 4.2.1 Floating Point Primitives .............................................................................. 96 4.2.2 Microblaze Implementation ........................................................................ 100 vii 4.2.2.1 Base System Builder .......................................................................... 106 4.2.2.2 DVI IIC PLB Interface. .................................................................... 116 4.2.2.3 N64 PLB controller interface. .......................................................... 117 4.2.2.4 Graphics Pipeline Registers PLB interface. ................................... 119 4.2.3 Graphics Pipeline Implementation ............................................................ 120 4.2.3.1 Floating Point Conversion and Matrix Selector ............................. 121 4.2.3.2 Matrix Transformation and Selection ............................................. 122 4.2.3.3 Cohen-Sutherland Clipping. ............................................................ 123 4.2.3.4 Bresenham’s Line Rasterizer ........................................................... 124 4.2.3.5 Frame Buffer and the ZBT Memory Controller ............................ 125 4.2.3.6 VGA Display Interface and the Line Doubler. ............................... 125 4.3 GRAPHICS PIPELINE FUNCTIONAL TESTBENCH ............................. 128 4.4 GPU SYNTHESIS ........................................................................................... 134 4.4.1 Xilinx EDK and Microblaze ....................................................................... 134 4.4.2 ISE and Full GPU Synthesis ....................................................................... 136 4.4.3 Synthesis Results .......................................................................................... 137 4.5 SOFTWARE BASED HARDWARE TESTING .......................................... 138 5.0 SUMMARY, CONCLUSIONS, AND FUTURE WORK ..................................... 144 5.1 SUMMARY AND CONCLUSIONS .............................................................. 144 5.2 FUTURE WORK ............................................................................................. 146 5.2.1 Feature Additions .......................................................................................