Implementation of a Design Rule Checker for Silicon Wafer Fabrication by Evren R. Onver Submitted to the Department of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degree of Master of Engineering in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology May 1994 © Massachusetts Institute of Technology 1994. All rights reserved. 7aa 0 A· 'Sf Author Department of ElectricalEngineering and Computer Science May 16, 1994 Certified by , .- - t, -/ Donald E. Troxel Professor of Electrical Engineering Co-Thesis Supervisor · - . rA^;-;s g, L111vu UYu Accepted by ; Implementation of a Design Rule Checker for Silicon Wafer Fabrication by Evren R. Unver Submitted to the Department of Electrical Engineering and Computer Science May 16, 1994 In Partial Fulfillment of the Requirements for the Degree of Master of Engineering in Electrical Engineering and Computer Science ABSTRACT A table based design rule checker for silicon wafer processing has been implemented to verify the integrity of process flow recipes. Its goal is to enhance the safety of the operators and machines in the fabrication facilities while reducing the amount of time spent on the development and approval of process flows. The Design Rule Checker can be used either as an off-line process design aid, or as an on-line process monitoring tool. The first stages of integrating the Design Rule Checker into the graphical tree editor of the MIT Computer Aided Fabrication Environment (CAFE) have been completed. It is hoped that this new design rule checker will be both a powerful design tool for fabrication engineers as well as a useful utility for the software development personnel. Co-Thesis Supervisor: Donald E. Troxel Title: Professor of Electrical Engineering Co-Thesis Supervisor: Michael B. McIlrath Title: Research Scientist Implementation of a Design Rule Checker for Silicon Wafer Fabrication by Evren R. Unver Submitted to the Department of Electrical Engineering and Computer Science May 16, 1994 In Partial Fulfillment of the Requirements for the Degree of Master of Engineering in Electrical Engineering and Computer Science ABSTRACT A table based design rule checker for silicon wafer processing has been implemented to verify the integrity of process flow recipes. Its goal is to enhance the safety of the operators and machines in the fabrication facilities while reducing the amount of time spent on the development and approval of process flows. The Design Rule Checker can be used either as an off-line process design aid, or as an on-line process monitoring tool. The first stages of integrating the Design Rule Checker into the graphical tree editor of the MIT Computer Aided Fabrication Environment (CAFE) have been completed. It is hoped that this new design rule checker will be both a powerful design tool for fabrication engineers as well as a useful utility for the software development personnel. Co-Thesis Supervisor: Donald E. Troxel Title: Professor of Electrical Engineering Co-Thesis Supervisor: Michael B. McIlrath Title: Research Scientist Contents 1 INTRODUCTION ............................................................. 8 1.1 Motivation and Rationale............................................................. 10 1.2 Background ............................................................. 11 1.3 Design Rules ............................................................. 12 2 PREVIOUS WORK............................................................. 16 2.1 VLSI Design Rule Checking ............................................................. 16 2.2 Wenstrand's Model for Specification, Simulation and Design of Semiconductor Fabrication Processes ........................................ ..................... 17 2.3 Constraint Based Programming ........................................ ..................... 18 2.4 Supervisory Control Theory ..................... ........................................ 18 2.5 Duane Boning's Design Rule Checker ............................................................. 21 2.6 The Hitachi Process Flow Validation System ....................................................... 22 3 CIDM SOFTWARE OVERVIEW ............................................................. 25 3.1 GESTALT ........................................ ..................... 28 3.2 Schema . ............................................................ 29 3.3 Process Flow Representation . ............................................................ 29 3.3.1 PFR Syntax and Structure ........................................ ..................... 30 3.3.2 PFR Fabrication ............................................................. 34 3.3.3 Process Flow Tree vs. Task Flow Tree ........................................................... 34 4 APPROACH TO DESIGN RULE CHECKING ................................................... 36 4. 1 Finite State Machine Representation ..... ....................................... 36 4.2 Algorithm for design rule checking ............................................................. 37 4.2.1 Determine process wafers ........................................ ..................... 38 4.2.2 Check processing and update state................................................................ 41 4.2.3 Apply design rules......................................................................................... 43 4.2.4 Repeat in the body ........................................ ..................... 43 4.3 Important Features ............................................................. 46 4.3.1 Use of Database Objects............................................................. 46 4.3.2 Splits and Joins............................................................. 48 4.2.3 Use of the Task Flow Tree structure.............................................................. 49 5 OVERVIEW OF THE SOFTWARE ..................................................................... 51 5.1 Wafer representation ........................................................................................... 51 5.1.1I DRC-Wafer ................................................................................................... 51 5.1.2 Printed Representation ...................................... 53 5.1.3 The W afer List ........................................ 54 5.2 Operation Wafers ................................................................................................ 55 5.3 Updating the W afer State .................................................................................... 56 5.4 Program representation of the rules ..................................................................... 58 6 INTEGRATION INTO CAFE ................................................................................ 61 6.1 Command-line control ......................................................................................... 61 6.2 The Tree Editor ..................................... 62 6.3 Automatic checking............................................................................................. 64 7 CONCLUSION ....................................................................................................... 65 7.1 Contributions ..................................... 65 7.2 Future work ........................................................................................................ 66 7.2.1 Optimization ................................................................................................. 67 7.2.2 Further Integration into CAFE...................................... 67 7.2.3 Expandedfunctionality ................................................................................. 68 APPENDIX A: DEVELOPER'S GUIDE ..................................... 70 A. 1 How to add a rule .................. ......... ............................................70 A. 1.1 The Structure of the Safety Rules ...................................... 70 A. 1.2 The Structure of the W afer State operations................................................. 72 A.2 Additional wafer state ......................................................................................... 73 APPENDIX B: PROGRAM CODE ........................................................................... 74 BIBLIOG RAPH Y ....................................................................................................... 90 List of Figures Figure 1-1: The fabrication process sequence of integrated circuits ................................. 9 Figure 2-1: (a) Generator plant and (b) Input/Output plant ........................................ 19 Figure 2-2: Plant with Controller feedback loop ............................................................. 20 Figure 2-3: Supervisory control scheme......................................................................... 21 Figure 2-4: Example of process flow mistake................................................................. 24 Figure 3-1: CAFE system architecture ........................................................................... 27 Figure 3-2: Process Flow Tree and Task Flow Tree ....................................................... 35 Figure 4-1: FSM Approach to Design Rules ................................................................ 37 Figure 4-2: (a) Wafer, (b) Waferset, (c) Waferlot data types ......................................... 40 Figure 4-3: Wafer state at each process node ................................................. 42 Figure 4-4: Sample warning