Compact Models for Future Generation CMOS By Darsen Duane Lu A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering — Electrical Engineeing and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Chenming Hu, Chair Professor Ali M. Niknejad Professor Sourav Chatterjee Spring 2011 Compact Models for Future Generation CMOS Copyright 2011 by Darsen Duane Lu Abstract Compact Models for Future Generation CMOS by Darsen Duane Lu Doctor of Philosophy in Engineering — Electrical Engineeing and Computer Sciences University of California, Berkeley Professor Chenming Hu, Chair Multiple-gate MOSFETs with superior short channel control are expected to replace planar CMOS in the near future. An accurate and computationally efficient compact tran- sistor model is necessary to simulate circuits in multiple-gate MOSFET technologies. In this dissertation research, a compact multiple-gate MOSFET model, BSIM-MG is devel- oped. BSIM-MG includes independent multi-gate compact model BSIM-IMG and common multi-gate compact model BSIM-CMG. We focus on BSIM-IMG for multiple-gate MOS- FETs with independent front- and back-gates. The basic formulations for surface potential, drain current and charge are derived and verified against TCAD simulations with excellent agreements. The model preserves important property of multi-gate MOSFETs such as vol- ume inversion. Non-ideal effects including short channel effects, length dependent back-gate coupling, transport models, leakage currents, parasitic resistances and capacitances, tem- perature effects and self heating are considered in the model. The model expressions are carefully formulated so that the symmetry of the source and drain is preserved. Rules for maintaining symmetry are discussed in this dissertation. For the common multi-gate transistor model BSIM-CMG, the basic expressions have been improved so that it is compatible with a novel non quasi-static effects modeling technique — charge segmentation. In addition, a parasitic source/drain resistance model is devel- oped, including three components: the contact resistance, the spreading resistance, and the bias-dependent extension resistance. Both BSIM-CMG and BSIM-IMG models are verified against TCAD and measured data. The use of the FinFET compact model to model manufacturing variation in a FinFET technology is further explored. The model matches measured data well for both the nominal case and the statistical distribution for NMOS threshold voltage as well as the read static noise margin. A non-Gaussian threshold voltage distribution is observed for nFET devices, and the compact model successfully captures the distribution. We further outlined and demonstrated a Monte-Carlo based procedure for designing FinFET SRAM cells using the extracted variation information. 1 Technology scaling has enabled numerous CMOS analog circuits for low cost radio- frequency applications. The modeling of MOSFET thermal noise becomes very important. In the final part of this dissertation research, a new thermal noise model is developed for the industry standard BSIM4 model that enhances the existing thermal noise formulation in BSIM4. The model is verified against a segmented channel MOSFET model as well as measured data. It is implemented in Berkeley SPICE3 and is ready for industry use. A method to port the model to BSIM-MG for thermal noise modeling in multi-gate MOSFETs is also presented. 2 Dedicated to my family i Contents Contents ii Acknowledgements vi 1 Introduction 1 1.1 CMOS Scaling and its Challenges . ..................... 1 1.2Multi-gateMOSFET—theFutureCMOSTransistorStructure....... 2 1.2.1 AdvantagesofMulti-gateMOSFETs.................. 2 1.2.2 VariousFlavorsofMulti-gateMOSFET................ 2 1.3Multi-gateCMOSModeling........................... 3 1.3.1 BSIM-MG: A BSIM-family Model for Multi-gate MOSFET . 3 1.3.2 BSIM-IMGandBSIM-CMG....................... 5 1.4 Modeling Parasitic Resistances and Capacitances in the FinFET Multi-Gate Device....................................... 5 1.5VariationinFinFETSRAMCells........................ 6 1.6 Thermal Noise Modeling for Planar and Multi-gate Transistors ........ 7 1.7 Dissertation Goals and Outline ......................... 7 2 Basic Formulations of Multiple-Gate MOSFET Compact Models 9 2.1CoreModelsofBSIM-CMGandBSIM-IMG.................. 9 2.2 Modeling Double-gate Fully-depleted SOI MOSFETs with BSIM-IMG .... 10 2.3CoreModelofBSIM-IMG............................ 11 2.3.1 Modeling Framework ........................... 11 2.3.2 Explicit Approximation for Surface Potential .............. 11 2.3.3 DrainCurrentModel........................... 15 2.3.4 CapacitanceModel............................ 23 2.4CoreModelofBSIM-CMG............................ 24 2.4.1 Background................................ 24 2.4.2 Simple Non Charge Sheet I-V Model .................. 26 2.5 Real Device Effects and Source Drain Symmetry ................ 28 2.6ModelConvergence................................ 30 ii 2.7 Computational Efficiency Study ......................... 33 2.7.1 EvaluationMethodology......................... 33 2.7.2 Computational Efficiency of Surface Potential Calculation in BSIM- CMG.................................... 35 2.7.3 Computational Efficiency of Surface Potential Calculation in BSIM-IMG 35 2.8CircuitSimulationusingBSIM-IMGandBSIM-CMG............. 37 2.8.1 FinFETSRAMwithBack-gateDynamicFeedback.......... 37 2.8.2 Dynamic Threshold Voltage Tuning to Combat Variation in Back- gatedFDSOI............................... 38 2.9 Summary ..................................... 38 3 Symmetry in MOSFET Compact Models 41 3.1 Symmetry Definition and the Gummel Symmetry Test ............ 41 3.2SymmetryofMOSFETCoreModels...................... 42 3.2.1 SquareLawModel............................ 42 3.2.2 BSIM-IMGCoreModel......................... 43 3.2.3 BSIM-CMGCoreModel......................... 43 3.3 Rules for Incorporating Real Device Effects ................... 44 3.4 Relation of Source/Drain Swapping and Continuity .............. 48 3.5 Discussion on the Formulation of Effective Drain-to-source Voltage ...... 49 3.6 Summary ..................................... 49 4 Modeling of FinFET Parasitic Source and Drain Resistances 52 4.1 FinFET Device Structure and Symbol Definitions . ............ 53 4.2 Modeling of Geometry Dependent Source/Drain Resistances in FinFETs . 57 4.2.1 ContactResistance............................ 57 4.2.2 Spreading Resistance ........................... 60 4.2.3 ExtensionResistance........................... 62 4.3Verification.................................... 65 4.3.1 TCADSimulationSetup......................... 66 4.3.2 Device Optimization ........................... 66 4.3.3 Extraction of Source and Drain Resistances .............. 69 4.4Discussion..................................... 73 4.5Conclusion..................................... 76 5 Compact Modeling of Variation in FinFET SRAM Cells 77 5.1Introduction.................................... 77 5.2SRAMDesignConsiderations.......................... 78 5.3FinFETSRAMAdvantagesandChallenges.................. 81 5.4 Modeling Vth Variation due to Gate Length and Fin Thickness Variation . 81 5.5 Modeling Variation in SRAM Cells ....................... 82 iii 5.6StatisticalDesignProcedureforFinFETSRAMs............... 83 5.7ExperimentalVerification............................ 85 5.7.1 DeviceFabrication............................ 85 5.7.2 Nominal Parameter Extraction ..................... 85 5.7.3 AdjustmentforSRAMFETs...................... 85 5.7.4 Calibration of Variation ......................... 85 5.8FinFETSRAMCellDesignExercise...................... 89 5.8.1 DesignCriterionforReadandWriteOperations............ 89 5.8.2 Cell Optimization ............................. 89 5.9SensitivityAnalysis................................ 91 5.10 Improved Variation Calibration Method .................... 91 5.11Conclusion..................................... 94 6 Thermal Noise Modeling for BSIM4 and BSIM-MG 95 6.1Review:BSIM4Thermalnoisemodel...................... 96 6.1.1 Charge-BasedThermalNoiseModel................... 96 6.1.2 HolisticThermalNoiseModel...................... 97 6.1.3 VerificationwithCircuitSimulation................... 101 6.2DerivationofNewThermalNoiseModel.................... 101 6.2.1 DrainNoise................................ 103 6.2.2 InducedGateNoise............................ 105 6.2.3 Correlation................................ 106 6.2.4 Verification................................ 107 6.3ThermalNoiseintheWeakInversionRegion.................. 109 6.3.1 Derivation of Thermal Noise Expressions Valid in All Regions of Op- eration................................... 112 6.3.2 Verifications................................ 115 6.4 Implementing Correlated Noise Sources in SPICE3 .............. 118 6.4.1 Implementation.............................. 118 6.4.2 Verification................................ 119 6.5 Modeling Excess Noise for Short Channel Devices ............... 121 6.6 Thermal Noise Modeling for BSIM-MG ..................... 125 6.7ConclusionandFutureWork........................... 125 7 Conclusions 127 7.1 Summary and Future Research Directions ................... 127 7.1.1 IndependentMulti-gateMOSFETModelBSIM-IMG......... 127 7.1.2 CommonMulti-gateMOSFETModelBSIM-CMG.......... 128 7.1.3 SymmetryofMOSFETCompactModels................ 128 7.1.4 Modeling Source and Drain Resistances for the FinFET ........ 129 7.1.5