NS32532-20/NS32532-25/NS32532-30 High-Performance 32-Bit Microprocessor May 1991 NS32532-20/NS32532-25/NS32532-30 High-Performance 32-Bit Microprocessor General Description Features The NS32532 is a high-performance 32-bit microprocessor Y Software compatible with the Series 32000 family in the Series 32000É family. It is software compatible with Y 32-bit architecture and implementation the previous microprocessors in the family but with a greatly Y 4-GByte uniform addressing space enhanced internal implementation. Y On-chip memory management unit with 64-entry The high-performance specifications are the result of a four- translation look-aside buffer stage instruction pipeline, on-chip instruction and data Y 4-Stage instruction pipeline caches, on-chip memory management unit and a signifi- Y 512-Byte on-chip instruction cache cantly increased clock frequency. In addition, the system Y 1024-Byte on-chip data cache interface provides optimal support for applications spanning Y High-performance bus a wide range, from low-cost, real-time controllers to highly Ð Separate 32-bit address and data lines sophisticated, general purpose multiprocessor systems. Ð Burst mode memory accessing The NS32532 integrates more than 370,000 transistors fab- Ð Dynamic bus sizing ricated in a 1.25 mm double-metal CMOS technology. The Y Extensive multiprocessing support advanced technology and mainframe-like design of the de- Y Floating-point support via the NS32381 or NS32580 vice enable it to achieve more than 10 times the throughput Y m of the NS32032 in typical applications. 1.25 m double-metal CMOS technology Y 175-pin PGA package In addition to generally improved performance, the NS32532 offers much faster interrupt service and task switching for real-time applications. Block Diagram TL/EE/9354±1 FIGURE 1 Series 32000É and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/EE/9354 RRD-B30M105/Printed in U. S. A. Table of Contents 1.0 PRODUCT INTRODUCTION 3.0 FUNCTIONAL DESCRIPTION (Continued) 2.0 ARCHITECTURAL DESCRIPTION 3.1.3 Instruction Pipeline 3.1.3.1 Branch Prediction 2.1 Register Set 3.1.3.2 Memory Mapped I/O 2.1.1 General Purpose Registers 3.1.3.3 Serializing Operations 2.1.2 Address Registers 3.1.4 Slave Processor Instructions 2.1.3 Processor Status Register 3.1.4.1 Regular Slave Instruction Protocol 2.1.4 Configuration Register 3.1.4.2 Pipelined Slave Instruction Protocol 2.1.5 Memory Management Registers 3.1.4.3 Instruction Flow and Exceptions 2.1.6 Debug Registers 3.1.4.4 Floating-Point Instructions 2.2 Memory Organization 3.1.4.5 Custom Slave Instructions 2.2.1 Address Mapping 3.2 Exception Processing 3.2.1 Exception Acknowledge Sequence 2.3 Modular Software Support 3.2.2 Returning from an Exception Service Procedure 2.4 Memory Management 3.2.3 Maskable Interrupts 2.4.1 Page Tables Structure 3.2.3.1 Non-Vectored Mode 2.4.2 Virtual Address Spaces 3.2.3.2 Vectored Mode: Non-Cascaded Case 2.4.3 Page Table Entry Formats 3.2.3.3 Vectored Mode: Cascaded Case 2.4.4 Physical Address Generation 3.2.4 Non-Maskable Interrupt 2.4.5 Address Translation Algorithm 3.2.5 Traps 3.2.6 Bus Errors 2.5 Instruction Set 3.2.7 Priority Among Exceptions 2.5.1 General Instruction Format 3.2.8 Exception Acknowledge Sequences: 2.5.2 Addressing Modes Detailed Flow 2.5.3 Instruction Set Summary 3.2.8.1 Maskable/Non-Maskable Interrupt Sequence 3.0 FUNCTIONAL DESCRIPTION 3.2.8.2 Abort/Restartable Bus Error Sequence 3.1 Instruction Execution 3.2.8.3 SLAVE/ILL/SVC/DVZ/FLG/BPT/UND 3.1.1 Operating States Trap Sequence 3.1.2 Instruction Endings 3.2.8.4 Trace Trap Sequence 3.1.2.1 Completed Instructions 3.1.2.2 Suspended Instructions 3.1.2.3 Terminated Instructions 3.1.2.4 Partially Completed Instructions 2 Table of Contents (Continued) 3.0 FUNCTIONAL DESCRIPTION (Continued) 4.0 DEVICE SPECIFICATIONS (Continued) 3.2.8.5 Integer-Overflow Trap Sequence 4.4.1 Definitions 3.2.8.6 Debug Trap Sequence 4.4.2 Timing Tables 3.2.8.7 Non-Restartable Bus Error Sequence 4.4.2.1 Output Signals: Internal Propagation 3.3 Debugging Support Delays 4.4.2.2 Input Signal Requirements 3.3.1 Instruction Tracing 3.3.2 Debug Trap Capability 4.4.3 Timing Diagrams 3.4 On-Chip Caches APPENDIX A: INSTRUCTION FORMATS 3.4.1 Instruction Cache (IC) B: COMPATIBILITY ISSUES 3.4.2 Data Cache (DC) B.1 Restrictions on Compatibility 3.4.3 Cache Coherence Support B.2 Architecture Extensions 3.4.4 Translation Look-aside Buffer (TLB) B.3 Integer-Overflow Trap 3.5 System Interface B.4 Self-Modifying Code 3.5.1 Power and Grounding 3.5.2 Clocking B.5 Memory-Mapped I/O 3.5.3 Resetting C: INSTRUCTION SET EXTENSIONS 3.5.4 Bus Cycles C.1 Processor Service Instructions 3.5.4.1 Bus Status C.2 Memory Management Instructions 3.5.4.2 Basic Read and Write Cycles C.3 Instruction Definitions 3.5.4.3 Burst Cycles 3.5.4.4 Cycle Extension D: INSTRUCTION EXECUTION TIMES 3.5.4.5 Interlocked Bus Cycles D.1 Internal Organization and Instruction 3.5.4.6 Interrupt Control Cycles Execution 3.5.4.7 Slave Processor Bus Cycles D.2 Basic Execution Times 3.5.5 Bus Exceptions D.2.1 Loader Timing 3.5.6 Dynamic Bus Configuration D.2.2 Address Unit Timing 3.5.6.1 Instruction Fetch Sequences D.2.3 Execution Unit Timing 3.5.6.2 Data Read Sequences D.3 Instruction Dependencies 3.5.6.3 Data Write Sequences D.3.1 Data Dependencies 3.5.7 Bus Access Control D.3.1.1 Register Interlocks 3.5.8 Interfacing Memory-Mapped I/O Devices D.3.1.2 Memory Interlocks 3.5.9 Interrupt and Debug Trap Requests D.3.2 Control Dependencies 3.5.10 Cache Invalidation Requests 3.5.11 Internal Status D.4 Storage Delays D.4.1 Instruction Cache Misses 4.0 DEVICE SPECIFICATIONS D.4.2 Data Cache Misses 4.1 Pin Descriptions D.4.3 TLB Misses 4.1.1 Supplies D.4.4 Instruction and Operand Alignment 4.1.2 Input Signals D.5 Execution Time Calculations 4.1.3 Output Signals D.5.1 Definitions 4.1.4 Input/Output Signals D.5.2 Notes on Table Use 4.2 Absolute Maximum Ratings D.5.3 Teff Evaluation 4.3 Electrical Characteristics D.5.4 Instruction Timing Example 4.4 Switching Characteristics D.5.5 Execution Timing Tables D.5.5.1 Basic and Memory Management Instructions D.5.5.2 Floating-Point Instructions, CPU Portion 3 List of Illustrations CPU Block Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1 NS32532 Internal Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-1 Processor Status Register (PSR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-2 Configuration Register (CFG) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-3 Page Table Base Registers (PTBn) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-4 Memory Management Control Register (MCR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-5 Memory Management Status Register (MSR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-6 Debug Condition Register (DCR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-7 Debug Status Register (DSR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-8 NS32532 Address Mapping ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-9 NS32532 Run-Time Environment ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-10 Two-Level Page Tables ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-11 Page Table Entries (PTE's) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-12 Virtual to Physical Address Translation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-13 General Instruction Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-14 Index Byte Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-15 Displacement Encodings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2-16 Operating States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-1 NS32532 Internal Instruction Pipeline ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-2 Memory References for Consecutive Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-3 Memory References after Serialization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-4 Regular Slave Instruction Protocol: CPU Actions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-5 ID and Operation Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-6 Slave Processor Status Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-7 Instruction Flow in Pipelined Floating-Point Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-8 Interrupt Dispatch Table ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-9 Exception Acknowledge Sequence: Direct-Exception Mode Disabled ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-10 Exception Acknowledge Sequence: Direct-Exception Mode Enabled ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3-11 Return From Trap (RETTn) Instruction Flow: Direct-Exception Mode Disabled ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ