MC92604 Dual Gigabit Ethernet Transceiver Reference Manual MC92604RM Rev. 1, 06/2005 Contents Paragraph Page Number Title Number About This Book Audience ........................................................................................................................i-xiii Organization...................................................................................................................i-xiii Suggested Reading......................................................................................................... i-xiv General Information............................................................................................... i-xiv Related Documentation ......................................................................................... i-xiv Conventions .................................................................................................................... i-xv Signals............................................................................................................................. i-xv Chapter 1 Introduction 1.1 Overview.......................................................................................................................... 1-1 1.2 Features............................................................................................................................ 1-2 1.3 Block Diagram................................................................................................................. 1-3 1.4 References........................................................................................................................ 1-5 Chapter 2 Transmitter 2.1 Transmitter Block Diagram ............................................................................................. 2-2 2.2 Transmitter Interface Signals........................................................................................... 2-2 2.3 Transmitter Interface Configuration ................................................................................ 2-4 2.3.1 Transmit Driver Operation........................................................................................... 2-5 2.3.2 Repeater Mode Operation............................................................................................ 2-5 2.4 Backplane Application Modes (COMPAT = Low).......................................................... 2-5 2.4.1 Transmitting Uncoded Data—8-/4-Bit Modes ............................................................ 2-6 2.4.2 Transmitting Coded Data—10-/5-Bit Modes .............................................................. 2-7 2.5 Ethernet Compliant Applications Modes (COMPAT = High)......................................... 2-9 2.5.1 Transmitting Uncoded Data—GMII or RGMII Modes............................................... 2-9 2.5.1.1 Auto-Negotiation Process........................................................................................ 2-9 2.5.1.2 Ethernet Data Transmission Process...................................................................... 2-10 2.5.2 Transmitting Coded Data—TBI or RTBI Modes ...................................................... 2-11 2.6 Transmitter Redundant Link Operation ......................................................................... 2-12 MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1 Freescale Semiconductor iii Paragraph Page Number Title Number Chapter 3 Receiver 3.1 Receiver Block Diagram.................................................................................................. 3-2 3.2 Receiver Interface Signals ............................................................................................... 3-3 3.3 Functional Description..................................................................................................... 3-5 3.3.1 Input Amplifier ............................................................................................................ 3-5 3.3.2 Transition Tracking Loop and Data Recovery............................................................. 3-6 3.3.3 8B/10B Decoder .......................................................................................................... 3-6 3.3.4 Half-Speed Mode......................................................................................................... 3-6 3.3.5 Repeater Mode............................................................................................................. 3-6 3.3.6 Receiver Redundant Link Operation ........................................................................... 3-7 3.4 Receiver Interface Configuration..................................................................................... 3-7 3.5 Data Alignment Configurations....................................................................................... 3-8 3.5.1 Non-Aligned Mode (BSYNC = Low) ......................................................................... 3-8 3.5.2 Byte-Aligned Mode (BSYNC = High) ........................................................................ 3-8 3.5.3 Word Synchronization ............................................................................................... 3-10 3.5.3.1 Word Synchronization Method.............................................................................. 3-10 3.6 Receiver Interface Timing Modes.................................................................................. 3-11 3.6.1 Recovered Clock Timing Mode (RCCE = High) ...................................................... 3-11 3.6.2 Reference Clock Timing Mode (RCCE = Low)........................................................ 3-12 3.7 Ethernet Compliant Applications Modes (COMPAT = High)....................................... 3-13 3.7.1 Interface to Ethernet MAC ........................................................................................ 3-13 3.7.1.1 GMII Operation ..................................................................................................... 3-14 3.7.1.2 TBI Operation........................................................................................................ 3-15 3.7.1.3 Double Data Rate Operation—RGMI and RTBI................................................... 3-16 3.7.2 Rate Adaption of Ethernet Packet Data Streams ....................................................... 3-17 3.7.2.1 Rate Adaption Method........................................................................................... 3-17 3.7.2.2 Configuration Context ........................................................................................... 3-17 3.7.2.3 Idle Context ........................................................................................................... 3-18 3.7.2.4 Data Context .......................................................................................................... 3-19 3.7.3 Error Handling ........................................................................................................... 3-19 3.7.3.1 Jumbo Frame Considerations ................................................................................ 3-19 3.8 Backplane Applications Modes (COMPAT = Low) ...................................................... 3-20 3.8.1 Byte Mode (Uncoded Data)....................................................................................... 3-20 3.8.2 10-Bit Mode (Coded Data) ........................................................................................ 3-21 3.8.2.1 Double Data Rate Operation—Backplane Applications ....................................... 3-22 MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1 iv Freescale Semiconductor Paragraph Page Number Title Number Chapter 4 Management Interface (MDIO) 4.1 MDIO Interface................................................................................................................ 4-1 4.2 MDIO Registers............................................................................................................... 4-2 4.2.1 MDIO RA 0—Control Register................................................................................... 4-3 4.2.2 MDIO RA 1—Status Register ..................................................................................... 4-4 4.2.3 MDIO RA 2 and 3—PHY Identifier Registers............................................................ 4-5 4.2.4 MDIO RA 4—Auto-Negotiation Advertisement Register .......................................... 4-6 4.2.5 MDIO RA 5—Auto-Negotiation Link Partner Ability Register ................................. 4-7 4.2.6 MDIO RA 6—Auto-Negotiation (AN) Expansion Register ....................................... 4-8 4.2.7 MDIO RA 7–14—Not Supported................................................................................ 4-8 4.2.8 MDIO RA 15—Extended Status Register................................................................... 4-8 4.2.9 MDIO RA 16 (Vendor Specific)—Permanent Configuration Control Register.......... 4-9 4.2.10 MDIO RA 17 (Vendor Specific)—Channel Configuration and Status Register ....... 4-11 4.2.11 MDIO RA 18 (Vendor Specific)—BERT Error Counter Register ............................ 4-12 Chapter 5 System Design Considerations 5.1 Reference Clock Configuration ....................................................................................... 5-1 5.2 Startup.............................................................................................................................. 5-2 5.3 Standby Mode .................................................................................................................