Direct Memory Access (DMA) Drive 1. CPU programs DMA Disk Main Operating Systems CPU the DMA controller controller memory controller Buffer Input/Output Address Count Control 4. Ack dr. Tomasz Jordan Kruk Interrupt when 2. DMA requests [email protected] done transfer to memory 3. Data transferred Bus Institute of Control & Computation Engineering p DMA modules control data exchange between main mamory and Warsaw University of Technology external devices, p usage of free bus time or (usually) delaying of the CPU for a one cycle from time to time to send a word by bus (cycle stealing and burst mode), p only one interrupt after the whole transfer, avoidance of context switches, Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 1/24 Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 3/24 Interrupts Revisited (hardware level) Input/Output Handling Interrupt 1. Device is finished controller Division of I/O devices: CPU 3. CPU acks interrupt Disk Keyboard 11 12 1 p block devices, read/write of each block possible independently, 10 2 9 3 8 4 Clock 7 5 2. Controller 6 Printer issues p character devices, deliver stream of characters without division into interrupt blocks, not addressable, without seek operation, Bus p communication/network devices sometimes distinguished as a p when an I/O device has finished the work given to it, it causes an interrupt by asserting a separate group because of their specificity, signal on a bus line that it has been assigned, p some devices, like timers, do not fit in to this classification scheme, p signal detected by the interrupt controller chip. If no other interrupts pending, the interrupt controller processes the interrupt immediately. If another one in progress or there is a simultaneous request on a higher-priority interrupt request line, continues to assert until serviced by the CPU. p the controller puts a number on the address lines and asserts a signal that interrupts the CPU, p that number used as an index into a table called the interrupt vector to start a corresponding interrupt service procedure, p the service procedure in certain moment acknowledges the interrupt by sending some value to some controller's port. That enables the controller to issue other interrupts. Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 2/24 Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 4/24 Differences in Input/Output Handling Communication with External Devices (I) Differencies in I/O handling: How processor communicates with control registers and how accesses external devices buffers. Two communication techniques: p complexity of service, 1. I/O ports, with each control register some port with established number p additional hardware support requirement, associated. Communication with special instructions: p priorization of services, IN REG, PORT p throughput unit, OUT PORT, REG p data representation, 2. memory-mapped I/O p device response type, p driver may be completely written in C, without any assembly code p error handling, pieces, because access only via standard read/write calls, p programming method. p no need for separate special protection mechanism, p faster testing of the contents of control registers, but p cache must be disabled for mapped region, p complicates the architecture with different type buses. Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 5/24 Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 7/24 Input/Output Programming Goals Communication with External Devices (II) p device independence, Two address One address space Two address spaces p uniform naming, 0xFFFF… Memory p error handling { the closer the hardware the better, p transfer type { synchronous/ asynchronous, I/O ports p buffering. 0 (a) (b) (c) a. separate I/O and memory space, b. memory-mapped I/O, c. hybrid solution, i.e. Pentium architecture: 640kB - 1MB addresses reserved for external devices still having I/O ports space 0 { 64K. Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 6/24 Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 8/24 Principles of I/O Software Interrupt-Driven I/O Three ways of I/O communication/ programming: copy_from_user(buffer, p, count); if (count == 0) { 1. programmed I/O (with polling, busy waiting behaviour), enable_interrupts( ); unblock_user( ); while ( printer_status_reg != READY) ; } else { 2. interrupt-driven I/O, * *printer_data_register = p[0]; *printer_data_register = p[i]; 3. I/O using DMA. scheduler( ); count = count − 1; i = i + 1; } acknowledge_interrupt( ); return_from_interrupt( ); (a) (b) An example of an interrupt-driven I/O: writing a string to the printer. a. code executed when the print system call is made, b. interrupt service procedure. Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 9/24 Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 11/24 Programmed I/O I/O Using DMA copy_from_user(buffer, p, count); /* p is the kernel bufer */ for (i = 0; i < count; i++) { /* loop on every character */ copy_from_user(buffer, p, count); acknowledge_interrupt( ); while (*printer_status_reg != READY) ; /* loop until ready */ set_up_DMA_controller( ); unblock_user( ); *printer_data_register = p[i]; /* output one character */ scheduler( ); return_from_interrupt( ); } return_to_user( ); (a) (b) An example: of I/O using DMA: printing a string. An example of programmed I/O: steps in printing a string. a. code executed when the print system call is made, b. interrupt service procedure. p advantage: reduction of number of interrupts from one per character to one per buffer printed, p not always the best method { aspects of transfer scope size and relative speed of CPU and DMA controller. Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 10/24 Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 12/24 I/O Software Layers Disk Access Performance I/O p seek time the time ti move the arm to the proper track, Layer reply I/O functions p rotational delay/latency the time for the proper sector to rotate under I/O User processes Make I/O call; format I/O; spooling the head, request p access time seek time + rotational latency, Device-independent Naming, protection, blocking, buffering, allocation software p seek time decides about performance, Device drivers Set up device registers; check status p important role of the cache memory (replacement algorithms LRU, LFU). Interrupt handlers Wake up driver when I/O completed Hardware Perform I/O operation Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 13/24 Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 15/24 Device-Independent I/O Software Disk Arm Scheduling Algorithms p uniform interfacing for device drivers, Because of requester: p under Unix: naming devices with usage of major and minor numbers, RSS random scheduling, p protection against unauthorized access, FIFO the most fair one, p providing a device-independent block size, PRI with priorities, p buffering mechanisms (example: double buffering), LIFO Last In First Out, locality and resource usage maximization, p management of accessability of devices, Because of service: p handling of allocation and releasing of devices, SSTF p management of resource to user allocation, shortest service time first with the smallest move of arm, SCAN elevator algorithm, the arm moves alternately in two directions (up p part of errors handling. and down) servicing all requests, C-SCAN cyclic SCAN, servicing during the move only in one direction with a fast return to the start position. Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 14/24 Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 16/24 Strip 0 Strip 1 Strip 2 Strip 3 Redundancy in Disk Service (a) Strip 4 Strip 5 RAIDStrip 6 SolutionsStrip 7 RAID level 0(RAID 1) Strip 8 Strip 9 Strip 10 Strip 11 RAID Redundant Array of Independent Disks { (formerly: Inexpensive) the name and classification originating from Berkeley University. Strip 0 Strip 1 Strip 2 Strip 3 Strip 0 Strip 1 Strip 2 Strip 3 RAID (b) Strip 4 Strip 5 Strip 6 Strip 7 Strip 4 Strip 5 Strip 6 Strip 7 p a technique of creation of virtual disks (with logical volumes), with some level 1 features related to reliability, efficiency and serviceability, from a group Strip 8 Strip 9 Strip 10 Strip 11 Strip 8 Strip 9 Strip 10 Strip 11 of disks, p data distributed over the matrix of disks, p mirroringBit 1 ,Bitfull 2 dataBitr edundancy3 Bit 4 , Bit 5 Bit 6 Bit 7 p redundancy used to improve fault tolerance, especially tolerance to p from the point of fault tolerance the best solution, physical medium damage. (c) RAID level 2 p expensive solution. p RAID as opposed to (before) SLED (Single Large Expensive Disk) or (now) JBOD (Just a Bunch of Disks). Bit 1 Bit 2 Bit 3 Bit 4 Parity (d) Strip 0 Strip 1 Strip 2 Strip 3 RAID level 3 (a) Strip 4 Strip 5 Strip 6 Strip 7 RAID level 0 Strip 8 Strip 9 Strip 10 Strip 11 Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 17/24 Faculty of E&IT, Warsaw University of Technology Operating Systems / Input/Output { p. 19/24 Strip 0 Strip 1 Strip 2