Tesla vs. Xeon Phi vs. Radeon A Compiler Writer’s Perspective Brent Leback, Douglas Miles, and Michael Wolfe The Portland Group (PGI) ABSTRACT: Today, most CPU+Accelerator systems incorporate NVIDIA GPUs. Intel Xeon Phi and the continued evolution of AMD Radeon GPUs make it likely we will soon see, and want to program, a wider variety of CPU+Accelerator systems. PGI already supports NVIDIA GPUs, and is working to add support for Xeon Phi and AMD Radeon. Here we explore the features common to all three types of accelerators, those unique to each, and the implications for programming models and performance portability from a compiler writer's and application writer’s perspective. KEYWORDS: Compiler, Accelerator, Multicore OpenACC directives. OpenMP has had great success for 1. Introduction its target domain, shared-memory multiprocessor and multicore systems. OpenACC has shown some initial Today’s high performance systems are trending success for a variety of applications [1, 2, 14, 15, 16, 17]. towards using highly parallel accelerators to meet It is just now being targeted for multiple accelerator types, performance goals and power and price limits. The most and our early experience is that it can be used to achieve popular compute accelerators today are NVIDIA GPUs. high performance for a single program across a range of Intel Xeon Phi coprocessors and AMD Radeon GPUs are accelerator systems. competing for that same market, meaning we will soon be Using directives for parallel and accelerator programming and tuning for a wider variety of host + programming divides the programming challenges accelerator systems. between the application writer and the compiler. Defining We want to avoid writing a different program for an abstract view of the target architecture used by the each type of accelerator. There are at least three current compiler allows a program to be optimized for very options for writing a single program that targets multiple different targets, and allows programmers to understand accelerator types. One is to use a library, which works how to express a program that can be optimized across really well if the library contains all the primitives your accelerators. application needs. Solutions built on class libraries with PGI has been delivering directive-based Accelerator managed data structures are really another method to compilers since 2009. The current compilers implement implement libraries, and again work well if the primitives the OpenACC v1.0 specification on 64-bit and 32-bit suit your application. The potential downside is that you Linux, OS/X and Windows operating systems, targeting depend on the library implementer to support each of your NVIDIA Tesla, Fermi and Kepler GPUs. PGI has targets now and in the future. demonstrated initial functionality on AMD Radeon GPUs A second option is to dive into a low-level, target and APUs, and Intel Xeon Phi co-processors. The PGI independent solution such as OpenCL. There are compilers are designed to allow a program to be compiled significant upfront costs to refactor your application, as for a single accelerator target, or to be compiled into a well as additional and continuing costs to tune for each single binary that will run on any of multiple accelerator accelerator. OpenCL, in particular, is quite low-level, and targets depending on which is available at runtime. They requires several levels of tuning to achieve high are also designed to generate binaries that utilize multiple performance for each device. accelerators at runtime, or even multiple accelerators from A third option is to use a high-level target different vendors. To make all these cases truly useful, independent programming model, such as OpenMP or the program must be written in a way that allows the CUG 2013 Proceedings 1 of 9 compiler to optimize for different architectures that have hits in the L2 cache, the result will take 12 cycles. An L3 common themes but fundamentally different parallelism cache hit will take 35-45 clock cycles, while missing structures. completely in the cache may take 250 or more cycles. There is additional overhead to manage multicore cache coherence for the L1 and L2 caches. 2. Accelerator Architectures Today GPU marketing literature often uses the term “GPU core” or equivalent. This is essentially a single precision Here we present important architectural aspects of (32-bit) ALU or equivalent. By this definition, an 8-core today’s multi-core CPUs and the three most common Sandy Bridge with AVX instructions has 64 GPU core- accelerators designed to be coupled to those CPUs for equivalents. technical computing: NVIDIA Kepler GPU [11], Intel Xeon Phi [13] and AMD Radeon GPU [12]. There are 2.2 NVIDIA Kepler GPU other accelerators in current use, such as FPGAs for An NVIDIA Kepler GPU has up to 15 SMX units, bioinformatics and data analytics, and other possible where each SMX unit corresponds roughly to a highly accelerator vendors, such as DSP units from Texas parallel CPU core. The SMX units execute warp- Instruments and Tilera, but these have not yet achieved a instructions, where each warp-instruction is roughly a 32- significant presence in the technical computing market. wide SIMD instruction, with predication. The warp is a fundamental unit for NVIDIA GPUs; all operations are processed as warps. The CUDA programming model uses 2.1 Common Multi-core CPU CUDA threads, which are implemented as predicated, For comparison, we present an architectural summary smart lanes in a SIMD instruction stream. In this section, of a common multi-core CPU. An Intel Sandy Bridge we use the term thread to mean a sequence of warp- processor has up to 8 cores. Each core stores the state of instructions, not a CUDA thread. The SMX units can up to 2 threads. Each core can issue up to 5 instructions store the state of up to 64 threads. Each SMX unit can in a single clock cycle; the 5 instructions issued in a single issue instructions from up to four threads in a single cycle, cycle can be a mix from the two different threads. This is and can issue one or two instructions from each thread. Intel’s Hyperthreading, which is an implementation of There are obvious structural and data hazards that would Simultaneous Multithreading. In addition to scalar limit the actual number of instructions issued in a single instructions, each core has SSE and AVX SIMD registers cycle. Instructions from a single thread are issued in- and instructions. An AVX instruction has 256-bit order. When a thread stalls while waiting for a result from operands, meaning it can process 8 single-precision memory or other slow operation, the SMX control unit floating point operations or 4 double-precision floating will select instructions from some other active thread. point operations with a single instruction. Each core has a The SMX clock is about 1.1 GHz. The SMX is also 32KB level-1 data cache and 32KB level-1 instruction pipelined, with 8 stages. cache, and a 256KB L2 cache. There is a L3 cache shared Each execution engine of the Kepler SMX has an across all cores which ranges up to 20MB. The CPU array of execution units, including 192 single precision clock rate ranges between 2.3GHz to 4.0GHz (in Turbo GPU cores (for a total of 2880 GPU cores on chip), plus mode). The core is deeply pipelined, about 14 stages. additional units for double precision, memory load/store The control unit for a modern CPU can issue and transcendental operations. The execution units are instructions even beyond the point where an instruction organized into several SIMD functional units, with a stalls. For instance, if a memory load instruction misses in hardware SIMD width of 16. This means that it takes two the L1 and L2 cache, its result won’t be ready for tens or cycles to initiate a 32-wide warp instruction on the 16- hundreds of cycles until the operand is fetched from main wide hardware SIMD function unit. memory. If a subsequent add instruction, say, needs the There is a two-level data cache hierarchy. The L1 result of that load instruction, the control unit can still data cache is 64KB per SMX unit. The L1 data cache is issue the add instruction, which will wait at a reservation only used for thread-private data. The L1 data cache is station until the result from the load becomes available. actually split between a normal associative data cache and Meanwhile, instructions beyond that add can be issued a scratchpad memory, with 25%, 50% or 75% of the and can even execute while the memory load is being 64KB selectively used as scratchpad memory. There is an processed. Thus, instructions are executed out-of-order additional 48KB read-only L1 cache, which is accessed relative to their appearance in the program. through special instructions. The 1.5MB L2 data cache is The deep, two- or three-level cache hierarchy reduces shared across all SMX units. The caches are small, the average latency for memory operations. If a memory relative to the large number of SIMD operations running data load instruction hits in the L1 cache, the result will be on all 15 SMX units. The device main memory ranges up ready in 4-5 clock cycles. If it misses in the L1 cache but to 6GB in current units and 12GB in the near future. CUG 2013 Proceedings 2 of 9 2.3 AMD Radeon GPU An AMD Radeon GPU has up to 32 compute units, 2.5 Common Accelerator Architecture Themes where each compute unit corresponds roughly to a simple There are several common themes across the Tesla, CPU core with attached vector units.