BiCMOS Digital Circuit Design Review of CMOS & NMOS Inverter Design - delay time - pair delay - driving large capacitive loads Features of BiCMOS Digital Circuit BiCMOS Inverters -basic type - delay time - improved type - full swing - design example a. size optimization b. driving large capacitive loads BiCMOS Gate Power-Supply Sensitivity - voltage scaling - low voltage gate I/O Interface - input - output - logic conversion Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-1 NMOS DIGITAL CIRCUITS Static inverters Load Vout ==> V in driver A B C IDS VGS=V(1) C B A VDS (driver) VDD Vth VDD D: in in Vout VGS=V(1) VGS=V(0) V(0) V(0) V(1) V(0) V(1) Vin ― Static power dissipation during Vout=V(0) Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-2 Switching Characteristics of CMOS Inverter CMOS inverter VDD VDD T 2 V (t) o t Vin(t) T1 CL +VDD Vin(t) 0 t +VDD 0.9VDD 0.1VDD t td tf tr Trajectory of n-transistor operating point during switching in CMOS inverter Input transition : X1 X2 Output transition: X2 X3 Vds=Vgs－Vt UNSATURATED SATURATED STATE STATE X2 Vgs=VDD Ids OPERATING POINT AFTER COMPLETION OF SWITCHING INITIAL OPERATING POINT X3 X1 0 VDD Vo(t) Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-3 Rise Time and Fall Time of CMOS Inverter > Equivalent Circuit V DD VDD > Fall p-DEVICE p-DEVICE t=0 t=0 I Vin ↑ c Ic Idsn R V c C o Vo n-DEVICE L n-DEVICE CL Vo ↓ SATURATION: VVoD≥ D− Vtn 0 < VV≤ − V (a) SATURATION: 0 DD tn > Rise VDD VDD p-DEVICE p-DEVICE Idsp Rc Vin ↓ I Ic Vo ↑ t=0 c Vo Vo n-DEVICE CL n-DEVICE CL LINEAR (b) SATURATION >tf = tf1 + tf2 ; fall time | tf1 | tf2 | Vo=0.9VDD Vo=0.1VDD Vo = VDD -Vtn | tf1 | tf2 | I = 0 DS()PMOS I DS()PMOS = 0 I DS()NMOS I in saturation DS()NMOS in triode Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-4 Fall Time (Cont.) t f Vo : 0.9 VDD V-DD Vtn NMOS in saturation region 2 d o β n C V ( V V)= 0 L d t 2 DD tn 0.9V t= 2CL DD f1 2 d o n V β (VDD -)Vtn ∫V DD V tn 2CL (Vtn 0.1 V)DD = 2 β n (VDD -)Vtn t f2 Vo : VDD Vtn 0.1 VDD NMOS in triode region d o β n 2 C V = [ 2(V V)V V ] L d t 2 gs tn ds ds VDD V DD V tn d Vo t= CL f2 n 2 β (VDD -)Vtn ∫ 0.1V DD Vo Vo 2(VDD -)Vtn Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-5 Fall Time (Cont.) CL 19V-DD 20Vtn t f2 = ln( ) β n (VDD -)Vtn VDD t=f t+f1 t f2 = 2CL β n (VDD -)Vtn V-0.1V 1 19V - 20V ×[ tn DD + ln( DD tn )] V-DD Vtn 2 VDD e.g. V=DD 5V,V=tp -1V, V=tn 1V 4CL t~f ~ β nVDD Rise time 4CL Similarly, t~r ~ β p VDD Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-6 Fall Time and Rise Time (Cont.) 4CL t f ≈ βn VDD 4CL t r ≈ βp[VDD For equally sized n and p devices βn = 2βp t t = r f 2 For tr =tf ⇒βp =βn ⇒Wp =2.5Wn For simplicity, 2 is used sometimes. t t = f df 2 t t = r dr 2 Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-7 Equivalent Circuit Equivalent Resistance ― 4CL tf = =ReqCL βnVDD ― 4 for minimum sized NMOS Req = βnVDD ― 4 R (PMOS)= ≈2.5R eq β V eq forn minimumDD sized PMOS Equivalent capacitance Ceq =Cgs of minimum sized transistors Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-8 Inverter-pair Delay >CMOS (a) Wp=2.5Wn;Wn and L are minimum size R eq Req Req 3.5Ceq 3.5Ceq Req Req Req tinv-pair =tf +tr =3.5Req Ceq +3.5Req Ceq =7Req Ceq (b) Wp=Wn; All minimum sized devices 2.5R eq 2.5Req 2.5Req 2Ceq 2Ceq Req Req Req tinv-pair =5Req Ceq +2Req Ceq =7Req Ceq W =2.5W ==> V =2.5V same delay time p n inv } Wp=Wn ==>Vinv =2.2V Vinv ~10% variation Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-9 Inverter-pair Delay (Cont.) Driving same size inverter L,W L,W L,W 2Ceq Req L,W L,W L,W L&W are minimum size Inverter-pair Delay=77Re qeC q= τ where τ = R e qeC q nL,mW nL,mW nL,mW nL,mW nL,mW nL,mW n R mnCeq m eq 2 Inverter-pair Delay = 7nCRe qeq= 7n 2 τ where τ = R e qeC q (Depends on channel length independent of channel width) gm µ u gs t Recall that W ==2 ()VV− CLg Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-10 Driving Large Capacitive Loads > CMOS L , f2W Lp, WP Lp, fWP p P ° ° ° CL Ln, Wn L , fW 2 n n Ln, f Wn (i) If Lp & Ln are minimum channel length , tinv-pair = 7f τ (ii) If Lp & Ln are not minimum channel length, additional calculation is required to obtain tinv-pair - Delay per stage (minimum L) (i) For Vin: (a) 3.5 τ (Wp= 2.5Wn), (b) 2 τ (Wp= Wn) (i) For Vin: (a) 3.5 τ (Wp= 2.5Wn), (b) 5 τ (Wp= Wn) > NMOS tinv-pair= 5f τ Delay per stage = f τ for Vin Delay per stage = 4f τ for Vin Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-11 Driving Large Capacitive Loads (Cont.) CL Let y = = fN Cg ( Cg : gate capacitance of the first stage inverter) lny = Nlna lny N = lna For N even , total delay N t = 7a = 3.5Na (CMOS) d 2 N (or) = 5a = 2.5Na (NMOS) 2 lny Delay α Nf = f lna (for both CMOS and NMOS) ==> For minimum td d lny ( f ) = 0 => obtain f = e to have the df lnf minimum value of Nf Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-12 Driving Large capacitive Loads (Cont.) Assuming f = e, then N = ln(y) Overall delay td (i) N even: tNd = 25. eτ (NMOS) or tNd = 35. eτ (CMOS) (ii) N is odd tNd =−[.25( 1)+1]eτ (NMOS) for tNd =−[.35( 1)+2]eτ (CMOS) } ∆Vin tNd =−[.25( 1)+4]eτ (NMOS) } for tNd =−[.35( 1)+5]eτ (CMOS) ∇Vin ** For optimum speed f=e=2.71828 But values from 2 to 10 may be used to obtain more flexibility and reduce cost(# of stages) Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-13 Features of BiCMOS Digital Circuit Combines CMOS and bipolar -CMOS Low power dissipation High density - Bipolar High drive capability Small swing logic “System on a chip” is possible - Mixed analog/digital Analog circuit can be incorporated - High voltage, high power interface (e.g. sensor, drive, ...) can be incorporated if special process is developed Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-14 BiCMOS Inverter Basic type + CMOS Bipolar(buffer) Physical structure NMOS PMOS NPN S G D S G D B E C n+ n+ p+ p+ p+ p+ n+ P-well N-well N-well p+-buried N+-buried N+-buried P-sub can be added to PMOS drain and NPN base increase latchup may be merged to reduce immunity (a) area (b) capacitance (c) # of contact Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-15 Pull-up of BiCMOS Inverter Basic type BiCMOS inverter • • VDD M βIDP ° 1 Q IDP 1 Input IDN βI M DN 2 CL Q2 Pull-up Input assume M2 & Q2 are off (initial condition) V -V V = 0 DD BE BE1 V BE t Input • VDD M βIDP Output ° 1 V -V I Q1 DD BE DP Output V V inv ° BE t CB CL+ CS1 tr td1 2 tdr CB is the capacitance at the Q1 base node CS1 is the capoacitance at the output node when CL= 0 VBECB td1 = ...time required to turn on Q IDN 1 (C +C ) tr Vinv L S1 = ...time required to change CL TO Vinv 2 βIDP ~ µpCOX W 2 where IDP ~ ( ) (Vdd-VBE-Vtp) 2 L M1 β vs. Ic β Ic t delay time t = t + r dr d1 2 Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-16 Pull-down of BiCMOS Inverter Pull-down M Q are off assume 1 & 1 initial condition VBE2= 0 Input V -V Input ° Output DD BE βI M2 DN VBE t Q CL+CS1 IDN 2 Output CB VDD-VBE Vinv VBE t td2 tf where CL is added capacitive load 2 t CS is the capacitance at the dr output node when CL= 0 V C V (CL+CS1) ~ BE B inv = + t tdf ~ + td2 f IDN βIDN 2 ~ µnCOX W 2 where IDN ~ ( ) (VDD-2VBE-Vtn) 2 L M2 ~ VSB ~ VBE β vs. Ic (body effect) β Ic Adjusting the size of M1 and M2, one can obtain tdr= tdf Tai-Haur Kuo, EE, NCKU, 1997 BiCMOS Circuit Design 3-17 Delay Time of CMOS Inverter CMOS inverter Input Output Cs2 is stray capacitance CL+CS2 Input VDD 0 t Output VDD Vinv. 0 t Vinv.