Hardware program simulator Item Type text; Thesis-Reproduction (electronic) Authors Navabi, Zainalabedin, 1952- Publisher The University of Arizona. Rights Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. Download date 07/10/2021 18:13:39 Link to Item http://hdl.handle.net/10150/347446 HARDWARE PROGRAM SIMULATOR by Zainalabedin Navabi V A Thesis Submitted to the Faculty of the DEPARTMENT OF ELECTRICAL ENGINEERING In Partial Fulfillment of the Requirements For the Degree of MASTER OF SCIENCE In the Graduate College THE UNIVERSITY OF ARIZONA - 1 9 7 8 STATEMENT BY AUTHOR This thesis has been submitted in partial fulfill­ ment of requirements for an advanced degree at The University of Arizona and is deposited in the University Library to be made available to borrowers under rules of the Library. Brief quotations from this thesis are allowable without special permission, provided that accurate acknowl­ edgment of source is made. Requests for permission for extended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the major department or the Dean of the Graduate College when in his judgment the proposed use of the material is in the inter­ ests of scholarship. in all other instances, however, permission must be obtained from the author. APPROVAL BY "THESIS DIRECTOR This thesis has been approved on the date shown below: arc FREDERICK' J, HILL Date bfessor of Electrical Engineering ACKNOWLEDGMENTS The author wishes to express his appreciation to Dr. F . J, Hill for hig guidance and encouragement during the preparation of this thesis. I thank my parents.for making everything possible in my career, and for their guidance. X also wish to thank my wife, Irma Navabi, for her patience and help in writing this thesis. TABLE OF CONTENTS Page LIST OF ILLUSTRATIONS .................. vi LIST OF TABLES ......... viii ABSTRACT ..... ..... ix CHAPTER 1. INTRODUCTION . , 1 2. AHPL CONTROL SEQUENCE SYNTAX FOR HPSIM PROGRAM . 4 2.1 Control Sequence BNF Grammar ............. 6 2.2 Major Modifications ........................ 6 3. HP SIM INPUT FILE SPECIFICATIONS .............. 9 3.1 AHPL Description File ........... 9 3.1.1 Basic Organization of a Module . 12 3.1.2 Symbols and Operators ............. 12 3.1.3 Declarations ............ 13 3.1.4 Standard Functions ................. 15 3.1.5 Locals, Semilocals, and Globals . 15 3.1.6 Comments . .......... 16 3.2 The Communication .Section F i l e ....... 18 4. DESIGN OF SIMULATOR PASS I . 19 4.1 The Interpreter Basic Structure ...... 19 4.2 Output of Pass I ............. 19 4.2.1 Symbol Reference Table (SRT) .... 20 4.2.2 Quadruple. Table CQTABLE) ........... 2 0 4.2.3 Step and QTABLE Relation Table (SQRTl , , ................... 23 4.2.4 Table of Temporary Symbols (TOTS) . 23 4.2.5 Next Executable Steps Table (NEST) ........................ 25 4.3 Interaction Between Phases of Pass-I . 25 4.4 Description of Phases of Pass-I ....... 29 4.4.1 Scanner ........ ........... 29 4.4.2 Symbol-Parser ............... 33 4.4.3 The Symbol-Manager Phase ...... 39 4.4.4 The Main-Parser Phase ....... 41 4.4.5 Semantics P h a s e .......... 46 iv V TABLE OF CONTENTS— Continued Page 5. DESIGN OF PASS II OF THE SIMULATOR .............. 4 9 5.1 User I/O Specification . 49 5„2 Function of the Second Pass ........ 49 5.3 Description of Subprograms of Pass II . 50 5.3.1 The Execution Operator Routine (EXEC \ ................... 52 5.3.2 The EXECUTION Routine . ...... .... 58 6. EXAMPLES OF USING HPSIM INTERPRETER ...... 67 6.1 A Digital P h a s e - M e t e r ............ 67 6.2 A Serial Communications Example . 73 6.3 Stack. Controller ................. 77 7. CPU TIME ANALYSIS .............. 83 8. CONCLUSIONS . 85 APPENDIX A. THE HPSIM INTERPRETER SOURCE CODE .... 86 APPENDIX B. THE TSP (SYNTAX) TABLE OF THE HPSIM PARSER ............................... 242 APPENDIX C, HPSIM PROGRAM OPERATION .................. 249 APPENDIX D. HPSIM PARAMETER L I M I T S ......... 256 APPENDIX E. HPSIM MODIFICATIONS FOR OTHER MACHINES ............... 257 REFERENCES . ........... ............... 259 9 LIST OF ILLUSTRATIONS Figure Page 2.1 Parsing organization .................... 5 2.2 The BNF grammar ......... ' 7 3.1 Input file organization........... 10 3.2 AHPL description section ............... 11 3.3 Referencing parts of an array ......... 14 3.4 Locals, semilocals, and globals in HPSIM . 17 4.1 The SRT table o r g a n i z a t i o n .................... 22 4.2 Pass-I output ................. 26 4.3 Interaction between phases of Pass-I ......... 30 4.4 The scanner phase ................ 31 4.5 The scanning process .................. 34 4.6 Symbol-parser flow c h a r t ...................... 38 4.7 Mainyparser routines .................... 4,3 4.8 A portion of TSP 44 5.1 Pass II block diagram ............. 51 5.2 The EXEC program flow chart ........... 53 5.3 Executable productions ................ 59 5.4 Loading the DPM . 62 5.5 LHS bif organization of identifiers in the DPM ‘ . 63 6.1 The digital phase-meter and its front end interface 68 6.2 Phase-meter flow chart . ............. 69 yi vii LIST OF ILLUSTRATIONS— Continued Figure Page 6.3 Phase-meter AHPL description ......... 70 6.4 The HP SIM output of the phase-meter ............ 71 6.5 HPSIM input file for the interface circuit . 74 6*6 HPSIM output listing for the interface circuit ............... 76 6.7 Sta,ck. Implementation , . ........... 78 6.8 AHPL description of the stack ......... 79 6.9 RAM AHPL sequence ................ 80 6.10 Lines and registers binary values of the stack example ............................ 81 6", 11 HP SIM initial information for the stack example 82 7,1 CPU time analysis for HP SIM . 84 C.l Running HP SIM/6400 253 C.2 Using HPSIM/10 (Timesharing) ......... 254 C ,3 Running HP SIM/10 batch ............. 255 LIST OF TABLES Table Page, 2.1 Operators ............... .. ...................... 8 4.1 SET columns, description of contents ..... 21 4.2 TOTS table description . , . 24 4.3 Scanner codes ..... ........................ 32 yiii ABSTRACT The hardware language AHPL was designed for describ­ ing digital systems in a mathematical form. Among other hardware languages AHPL became one of the most popular because of its one-to-one hardware correspondence. HPSIM,. Hardware Program SIMulator, is a digital system simulation program that uses AHPL as the source code language, and interprets it. The HPSIM program is a two pass interpreter. The first pass translates the source code into internal table form, and the second pass, the execution pass, executes the translated form of the source code. A complete description on how to use the HPSIM interpreter and a detailed explanation, with the help of flowcharts, is documented. Example programs and a complete listing of the interpreter program is included. CHAPTER 1 INTRODUCTION Hardware languages constitute a new approach to digital system design. Such languages with their supporting programs can facilitate the application of computer aided design to digital systems. One supporting program for hardware languages is a simulator. At the functional level, such a program will test the designed digital system, eliminating the designer's need to test and debug his circuit in the laboratory. HPSIM is a program of this sort. In hardware design languages a high level of detail might include the description of gates with delays associ­ ated, whereas a low level of detail might be description at the block, diagram level, AHPL II, 2], a hardware programing language, strikes a middle ground in descriptive levels. It is a clocked mode register transfer level language (RTL). The root of AHPL is APL 13]' which is noted for its ability to express very complex operations in compact form. AHPL inherits this trait, but always constrained by the necessity of a onfe-to-one correspondence with the actual hardware, because of these mentioned advantages, AHPL was chosen to be simulated by HPSIM (hardware program simulator). HPSIM is written in FORTRAN and has been implemented on the CDC-64 00 as well as the DEC 10. This program is a two pass interpreter, the first pass translates the source code into five executable tables, the second pass will begin executing the tables after the first pass has generated them. The input to the interpreter is an AHPL description of a circuit followed by data and printout request section. The output of the HPSIM program is a.list of the binary values at each clock period for any specified terminal or vector. The AHPL which is used as the input to HPSIM is a modified version of AHPL of Reference 2. This modification was necessary since the language AHPL as described in Reference 2 had some ambiguities and some symbols not available in ASCII. The modifications are very slight though, and the basic syntax of AHPL is unchanged. The HPSIM source code describes the hardware of the digital system. The. declarations of a HPSIM source code describe the basic elements of the circuit such as counters, adders, registers, bus-lines, etc. The AHPL description, on the other hand, describes the connections between these elements, Together, the declarations and description provide an exact software description Of the required hard­ ware . Normally an initial design of a digital circuit is run on HPSIRl and modified several times before a final design is reached. With final design in hand, building the hardware is just a matter of translating -the AHPL description to hardware. Using AHPL for designing digital systems and simulating those systems by HPSIM gives designer a good insight into the system, and corrections and modifi­ cations become as simple as adding, eliminating, or moving around AHPL statements in the description.