PHY Interface For the PCI Express, SATA, USB 3.1, DisplayPort, and Converged IO Architectures Version 5.1 ©2007 - 2018 Intel Corporation—All rights reserved. PHY Interface for PCI Express, SATA, USB 3.1, DisplayPort, and Converged IO Architectures, ver 5.1 Intellectual Property Disclaimer THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE. A COPYRIGHT LICENSE IS HEREBY GRANTED TO REPRODUCE AND DISTRIBUTE THIS SPECIFICATION FOR INTERNAL USE ONLY. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY OTHER INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY. INTEL CORPORATION AND THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF PROPRIETARY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION IN THIS DOCUMENT AND THE SPECIFICATION. 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All product names are trademarks, registered trademarks, or service marks of their respective owners Contributors Jeff Morris Jim Choate Michelle Jen Kaleb Ruof Andy Martwick Paul Mattos Bruce Tennant John Watkins Brad Hosler Dan Froelich Quinn Devine Jamie Johnston Matthew Myers Duane Quiet Su Wei Lim Todd Witter Bob Dunstan Hajime Nozaki Hooi Kar Loo Andrea Uguagliati Saleem Mohammad Peter Teng Poh Thiam Teoh Efraim Kugman Sue Vining Karthi Vadivelu Sathyanarayanan Gopal Daniel Resnick Tadashi Iwasaki Mineru Nishizawa Siang Lin Tan Tina Tahmoureszadeh Yoichi Iizuka Takanori Saeki Jake Li Rahman Ismail Andrew Lillie Zeeshan Sarwar Ben Graniello Frank Kavanagh Minxi Gao ©2007-2018 Intel Corporation – All rights reserved Page 2 of 161 PHY Interface for PCI Express, SATA, USB 3.1, DisplayPort, and Converged IO Architectures, ver 5.1 Dedicated to the memory of Brad Hosler, the impact of whose accomplishments made the Universal Serial Bus one of the most successful technology innovations of the Personal Computer era. ©2007-2018 Intel Corporation – All rights reserved Page 3 of 161 PHY Interface for PCI Express, SATA, USB 3.1, DisplayPort, and Converged IO Architectures, ver 5.1 Table of Contents 1 Preface .................................................................................................................................... 10 1.1 Scope of this Revision .................................................................................................... 10 1.2 Revision History ............................................................................................................. 10 2 Introduction ............................................................................................................................ 13 2.1 PCI Express PHY Layer ................................................................................................. 16 2.2 USB PHY Layer ............................................................................................................. 17 2.3 Converged IO PHY Layer .............................................................................................. 17 2.4 SATA PHY Layer ........................................................................................................... 17 2.5 Low Pin Count Interface and SerDes Architecture ......................................................... 18 3 PHY/MAC Interface .............................................................................................................. 19 4 PCI Express, USB, and Converged IO PHY Functionality ................................................... 28 4.1 Original PIPE Architecture ............................................................................................. 28 4.1.1 Transmitter Block Diagram (2.5 and 5.0 GT/s) ....................................................... 28 4.1.2 Transmitter Block Diagram (8.0/10/16 GT/s/32 GT/s) ........................................... 29 4.1.3 Receiver Block Diagram (2.5 and 5.0 GT/s) ........................................................... 29 4.1.4 Receiver Block Diagram (8.0/10.0/16/32 GT/s) ...................................................... 30 4.1.5 Clocking ................................................................................................................... 32 4.2 SerDes Architecture ........................................................................................................ 32 4.2.1 SerDes Architecture: Transmitter Block Diagram ................................................... 32 4.2.2 SerDes Architecture: Receiver Block Diagram ....................................................... 33 5 SATA PHY Functionality ...................................................................................................... 34 5.1 Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s) ..................................................... 35 5.2 Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s) ........................................................... 36 5.3 Clocking .......................................................................................................................... 36 6 PIPE Interface Signal Descriptions ........................................................................................ 37 6.1 PHY/MAC Interface Signals – Common for SerDes and Original PIPE ....................... 37 6.1.1 Data Interface .......................................................................................................... 37 6.1.2 Command Interface ................................................................................................. 40 6.1.3 Status Interface ........................................................................................................ 57 6.1.4 Message Bus Interface ............................................................................................. 64 6.1.4.1 Message Bus Interface Commands .................................................................. 64 6.1.4.2 Message Bus Interface Framing ....................................................................... 67 6.2 PHY/MAC Interface Signals – SerDes Architecture Only ............................................. 68 6.2.1 Data Interface .......................................................................................................... 68 6.2.2 Command Interface ................................................................................................. 68 6.3 PHY/MAC Interface Signals – Original PIPE Only ....................................................... 69 6.3.1 Data Interface .......................................................................................................... 69 6.3.2 Command Interface ................................................................................................. 72 6.4 External Signals – Common for SerDes and Original PIPE ........................................... 77 7 PIPE Message Bus Address Spaces ....................................................................................... 80 7.1 PHY Registers ................................................................................................................. 82 7.1.1 Address 0h: RX Margin Control0 ............................................................................ 83 7.1.2 Address 1h: RX Margin Control1 ............................................................................ 83 7.1.3 Address 2h: Elastic Buffer Control .......................................................................... 83 7.1.4 Address 3h: PHY RX Control0 ............................................................................... 84 7.1.5 Address 4h: PHY RX Control1 ............................................................................... 85 7.1.6 Address 5h: PHY RX Control2 ............................................................................... 85 7.1.7 Address 6h: PHY RX Control3 ............................................................................... 85 7.1.8 Address 7h: Elastic Buffer Location Update Frequency ......................................... 86 ©2007-2018 Intel Corporation – All rights reserved Page 4 of 161 PHY Interface for PCI Express, SATA, USB 3.1, DisplayPort, and Converged IO Architectures, ver 5.1 7.1.9 Address 8h: PHY RX Control4 ............................................................................... 86 7.1.10 Address 400h: PHY TX Control0 ............................................................................ 87 7.1.11 Address 401h: PHY TX Control1 ............................................................................ 87 7.1.12 Address 402h: PHY TX Control2 ............................................................................ 88 7.1.13 Address 403h: PHY TX Control3 ...........................................................................