Rewiring for Threshold Logic Circuit Minimization Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen §, Ching-Yi Huang Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C. §Department of Computer Science and Engineering, Yuan Ze University, Chung Li, Taiwan, R.O.C. Abstract—Recently, many works have been focused on syn- logic network synthesis and fault-tolerant threshold logic de- thesis, verification, and testing of threshold circuits due to the signs are interesting achievements recently [13][14][31]. Static rapid development in efficient implementation of threshold logic Timing Analysis of threshold logic circuits has been proposed circuits. To minimize the hardware cost of threshold circuit [25]. Besides, algorithms for the equivalence checking of implementation, this paper proposes a heuristic that consists of threshold logic circuits have been proposed [15]. Additionally, rewiring operations and a simplification procedure. Additionally, testing issue in threshold logic has also been addressed [16]. a subset of input vectors of a gate, called critical-effect vectors, Rewiring is a logic restructuring technique that has been are proved to be complete for formally verifying the equivalence well developed and widely applied in the traditional Boolean of two threshold logic gates, instead of the whole truth table circuits. It plays an important role in optimization of Boolean in this paper. This achievement can accelerate the equivalence networks [5]-[11][18]. Recently, Kuo et al. proposed the first checking of two threshold logic gates. The experimental results rewiring algorithm and a simplification procedure for threshold show that the proposed heuristic can efficiently reduce the cost. logic circuits [17]. Furthermore, in the simplification proce- 1 I. I NTRODUCTION dure, it proposed that if the critical-effect vectors (CEVs) and their additional brother vectors 2 of two threshold logic The research and development of threshold logic can be gates are identical, the two threshold logic gates are equivalent cast back to the 1960s. In 1961, an effective method to meaning that the simplification operation is valid. However, enumerating the threshold functions was proposed [28]. Later their rewiring algorithm only focused on circuit restructuring in 1962, an approximation method was proposed to determine and did not consider the cost minimization issue. Thus, in this the input weights and the threshold value of a threshold work, we propose a heuristic to rewire the circuit for mini- logic gate [27]. Besides, linear programming and tabulation mizing its weights and threshold value. Additionally, we also methods were introduced to determine whether a function prove that the CEVs, without including their brother vectors, can be represented in threshold logic or not [26]. Although are sufficient to justify the equivalence of two threshold gates. the related research on threshold logic was introduced in early days, threshold logic had a little impact on integrated II. P RELIMINARIES circuit designs due to the lack of efficient implementation. In A. Threshold logic past decades, however, threshold logic becomes popular due An LTG is a logic element whose output f is evaluated by to the rapid growth in nanotechnology-based devices, such EQ(1): as Resonant Tunneling Diodes (RTD) [2][3][12], Quantum n Cellular Automata (QCA) [23], Resistance switching devices 1 if x w ≥ T [20], Spin-based devices [1], and Single-Electron Transistor X i i i=1 (SET) [4][29][30][19][24]. Thus, threshold logic attracts more f(x1, x 2,...,x n) = n (1) attention than ever before. 0 if x w < T X i i i=1 Due to the tremendous impetus of VLSI technology, there are various implementations for threshold circuits, e.g., ca- where wi and T can be positive or negative numbers. pacitive linear threshold gates (LTGs) or RTD-based LTGs. Accordingly, different cost functions have been proposed to If the summation of corresponding weights wi of inputs evaluate the threshold circuits. In particularly, for the capacitive xi that are assumed to be 1 in an input vector is greater LTGs and RTD-based LTGs, the circuit area is proportional to than or equal to the threshold value T , the output f is 1. the weights and threshold value of an LTG [3]. Thus, in this Otherwise, the output f is 0. The model of an LTG is shown work, we adopt the summation of the weights and threshold in Fig. 1. A Boolean function realized by such an LTG is value of gates in threshold networks as the cost function when called a threshold function. Furthermore, a threshold function synthesizing a threshold logic circuit. may have many different representations that are represented as a weight-threshold vector hw1, w 2, . , w n; T i. A network On the other hand, not only the nanotechnology devices, that is composed of LTGs is called a threshold network. the design automation research has also triggered a vigorous Any Boolean function can be represented by a corresponding growth on threshold logic circuits. For example, the threshold threshold network. This work is supported in part by the National Science Council of Taiwan B. Critical-effect vectors under Grant NSC 102-2221-E-007-140-MY3, NSC 102-2221-E-155-087, NSC 101-2221-E-155-077, NSC 101-2628-E-007-005, and NSC 100-2628-E-007- An LTG has a critical-effect if and only if there exists an 031-MY3, and by the National Tsing Hua Unversity under Grant NTHU assignment such that the output changes from 1 to 0 when any 102N2726E1. 1The critical-effect vectors will be introduced in Section II. 978-3-9815370-2-4/DATE14/ c 2014 EDAA 2Please refer [17] for the definition of the brother vectors of CEVs. X1 a W1 a 1 X W2 b 2 … 3 f … b 2 1 1 1 Wi T f 1 4 f … c 1 1 Xi c 1 1 … W n d d Xn (a) (b) Fig. 1. An LTG model. a b c f Fig. 3. (a) An LTG. (b) A more efficient implementation. 0 0 0 0 0 0 1 0 a 2 0 1 0 0 OST MINIMIZATION ALGORITHM b 1 2 f 0 1 1 1 III. C c 1 1 0 0 1 1 0 1 1 The most commonly used approach to synthesizing a 1 1 0 1 1 1 1 1 threshold network is the ILP-based algorithm [31]. Although this algorithm is efficient to synthesize threshold networks Fig. 2. An LTG and its CEVs. for arbitrary functions, it actually achieves a local optimum of weights and threshold value under a given fanin number 3 one of its inputs in this assignment changes from 1 to 0. An constraint . Additionally, the algorithm tries to use fewer input assignment that satisfies the requirement of the critical- numbers of LTG to express a given function, which may effect for an LTG is called a critical-effect vector (CEV). For increase weights or threshold value. example, in Fig. 2, input assignments 011 and 100 are the For example, given a function f = ab + ac + ad . Fig. CEVs of LTG h2, 1, 1; 2 i. This is because changing any 1 to 0 3(a) is a corresponding threshold gate synthesized by the ILP- in these assignments will also change the output from 1 to 0. based algorithm. In contrast with Fig. 3(a), Fig. 3(b) is another EQ(2) shows the sufficient condition of an input assignment representation of the function f which is synthesized by the being a CEV, where n is the number of inputs in an LTG. rewiring algorithm. We can see that the summation of all the n weights and threshold value of Fig. 3(a) is 10, while that of Fig. x w = T (2) 3(b) is only 8. As a result, a synthesized threshold network with X i i fewer LTGs does not always achieve the globally minimal cost. =1 i In the following paragraphs, we first review some terminology Note that although in this example, the two CEVs both satisfy proposed in [17]. EQ(2), the CEVs of an LTG do not always satisfy this equation. Definition 1: An LTG is useless if and only if it outputs zero Since the concept of CEV plays an important role in the for all input combinations. proposed simplification flow, here we briefly introduce how to find the CEVs of an LTG. First, the weights are sorted Definition 2: An input in an LTG is critical if and only if this in a descending order. By the definition of a CEV, we know LTG will become useless after removing this input. that when any input in this assignment changes from 1 to 0, A. Overview the output changes from 1 to 0. Thus, in the procedure, we iteratively decrease the threshold value by the largest input Fig. 4 gives an overview of our algorithm. The input is weight and check the threshold value. If the threshold value a threshold network, and the output is a rewired threshold after the decrement becomes less than or equal to 0, the network with the reduced cost. We first identify a target wire procedure is terminated, and the threshold value is restored such that the cost can be reduced after removing the target for the next CEV. In each iteration of the procedure, when we wire and adding the rectification network. After the rewiring reduce the threshold value by wi, the corresponding input xi operations, the appearance of some LTGs may be changed. is set to 1; otherwise, it is set to 0. All the input assignments Thus, we perform the simplification procedure to minimize obtained in this procedure are the CEVs of this threshold gate.