Copyright © 2008 American Scientific Publishers Journal of All rights reserved Low Power Electronics Printed in the United States of America Vol.4, 1–12, 2008 Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power Andrew Bailey1, Ahmad Al Zahrani1, Guoyuan Fu2, Jia Di1 ∗, and Scott Smith2 1Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR72701, USA 2Department of Electrical Engineering, University of Arkansas, Fayetteville, AR72701, USA (Received: 14 June 2008; Accepted: 9 October 2008) This paper presents an ultra-low power circuit design methodology which combines the Multi- Threshold CMOS (MTCMOS) technique with quasi delay-insensitive (QDI) asynchronous logic, in order to solve the three major problems of synchronous MTCMOS circuits: (1) Sleep signal gener- ation, (2) storage element data loss during sleep mode, and (3) sleep transistor sizing. In contrast to most power reduction methods that result in area overhead, the QDIasynchronous MTCMOS circuits are usually smaller than their original versions. Moreover, QDIcircuits utilize handshaking protocols instead of clocks for circuit control, resulting in flexible timing requirements, which yields increased circuit robustness and allows for extreme supply voltage scaling to subthreshold region for further power reduction, without requiring any circuit modifications. This QDIasynchronous MTC- MOS methodology is used to design a 4-stage pipelined 8-bit × 8-bit unsigned multiplier, which is then compared against the original QDIdesign (i.e., without incorporating MTCMOS) and its syn- chronous version. All designs use the IBM 8RF-DM 0.13 m process. Results show 150× and 1.8× leakage power and active energy reductions on average in the QDIasynchronous MTCMOS design compared to the original QDIversion, respectively. Keywords: Ultra-Low Power, Quasi Delay-Insensitive Asynchronous Logic, MTCMOS, NULL Convention Logic. 1. INTRODUCTION In Ref.[1] several leakage minimization techniques are discussed and compared.Super Cutoff CMOS (SCCMOS) 2 With the current trend of semiconductor devices scaling under-drives (or over-drives) the sleep transistors, which into deep submicron region, design challenges that were gate the power to the circuit, to reduce leakage.Forced previously minor issues now become increasingly impor- Transistor Stacking3 takes advantage of stack effect, i.e., tant.Where in the past dynamic power has been the major leakage current decreases due to two or more series tran- factor in CMOS digital circuit power consumption, recently sistors that are turned off, by replacing a single transistor with the dramatic decrease of supply and threshold volt- by two transistors with half width.Sleepy Stack 4 combines ages, a significant growth in leakage power demands new forced stacking and sleep transistors to reduced delay.Input design methodologies for digital integrated circuits (ICs) to Vector Control5 analyzes the input vector dependence to meet the new power constraints.As one of the major com- shut down the circuit in standby mode.Optimal supply and ponents of leakage power, subthreshold leakage is caused threshold voltage scaling to achieve minimum energy oper- by the current flowing through a transistor even though it ation is discussed in Ref.[6].Variable Threshold voltage is supposedly turned off.The shrinking in transistor fea- subthreshold CMOS (VT-sub-CMOS) and subthreshold ture size exponentially increases the impact of subthreshold Dynamic Threshold voltage MOS (sub-DTMOS) are intro- leakage. duced in Ref.[7] to extend VTCMOS and DTMOS con- Many techniques have been proposed to control or cepts to subthreshold region.Adaptive Body Bias (ABB) minimize leakage power in deep submicron technology. is discussed in Ref.[8] to provide different biasing voltage to the bulk nodes of the transistors to change the threshold ∗Author to whom correspondence should be addressed. voltages (Vt).Pseudo-NMOS logic for subthreshold leak- Email: [email protected] age reduction is discussed in Ref.[9]. J. Low Power Electronics 2008, Vol. 4, No. 3 1546-1998/2008/4/001/012 doi:10.1166/jolpe.2008.181 1 Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power Bailey et al. In addition to the leakage reduction methods above, used in the designs; Section 4 discusses the implementa- Multi-Threshold CMOS,10 which reduces leakage power tion of MTCMOS in NCL circuits; Section 5 presents the by disconnecting the power supply from the circuit during designed circuits for comparison, the simulation results, the standby (or sleep) mode while maintaining high per- and the result analysis; and Section 6 draws conclusions formance in the active mode, has been widely adopted and describes related future research areas. in industry.MTCMOS incorporates transistors with two or more different threshold voltages in a circuit.Low threshold transistors offer fast speed but cost high leak- 2. MULTI-THRESHOLD CMOS FOR SYNCHRONOUS CIRCUITS age.In contrast, high threshold transistors suffer from reduced speed, but leak less current when turned off. There are multiple ways to implement MTCMOS in syn- MTCMOS combines these two types of transistors by uti- chronous circuits.One method is to use low threshold (low- lizing low threshold voltage transistors for circuit switch- Vt transistors to build the circuit units on critical paths, ing to preserve performance and high threshold voltage while those on non-critical paths use high threshold (high- transistors to gate the supply power in order to sup- Vt transistors.This allows the critical paths of a circuit press the subthreshold leakage.Section 2 describes MTC- to retain high speed, but use less leaky transistors in por- MOS implementation in synchronous circuits in more tions of the circuit with lower speed requirements.In addi- detail. tion to this path replacement methodology, there are two Another area of interest in low power research is asyn- other architectures of implementing MTCMOS.A large- chronous logic, which uses handshaking protocols instead scale technique investigated in Ref.[11] is to use low of clocks to control circuit behavior.As clock rates have threshold logic for all circuit functions and to gate the logic significantly increased while feature size has decreased, the with high threshold sleep transistors between the logic and clock has become a major problem of synchronous cir- the power source, as shown in Figure 1.The sleep transis- cuits.Hence, the 2005 edition of the International Technol- tors are controlled by the Sleep signal.During the active ogy Roadmap for Semiconductors (ITRS) report predicts mode, the Sleep signal is deasserted, causing both high- that asynchronous (clockless) paradigms will become more Vt transistors to turn on and provide a virtual power and widely used in the industry to increase circuit robustness, ground to the low-Vt logic.When the circuit is inactive, decrease power, and alleviate many clock related issues; Sleep signal is asserted, forcing both high-Vt transistors and the 2007 edition shows that asynchronous circuits account for 11% of chip area in 2008, compared to 7% in 2007, and estimates that asynchronous circuits will account VDD for 22% of chip area within the next 5 years, and 30% of chip area within the next 10 years.The advantages of asynchronous circuits include no clock tree, high power efficiency, flexible timing requirement, robust circuit opera- Reduce subthreshold tion, and low noise/emission.Asynchronous circuits, espe- SLEEP leakage during sleep mode cially quasi delay-insensitive asynchronous circuits, allow the power supply to be scaled to extremely low voltages, in some cases way below the threshold voltages of the Virtual VDD transistors, while maintaining the correct circuit opera- tion, and therefore have the potential to achieve ultra-low power consumption.As shown in this paper, by incorpo- Low-V CMOS Logic rating the MTCMOS technique into quasi delay-insensitive INPUTS t OUTPUTS asynchronous logic, the three primary drawbacks of syn- Maintain high performance during active mode chronous MTCMOS circuits, namely, Sleep signal gener- ation, storage element data loss during sleep mode, and Virtual GND sleep transistor sizing, can be eliminated.By implementing a performance enhancing technique named Early Comple- tion, a low active/leakage power, zero or even negative area SLEEP Reduce subthreshold overhead (i.e., the MTCMOS circuit is even smaller than leakage during sleep mode its original version), and robust digital circuit architecture can be achieved. This paper is organized as follows: Section 2 describes the synchronous MTCMOS architecture and its draw- backs; Section 3 introduces NULL Convention Logic (NCL), the quasi delay-insensitive asynchronous paradigm Fig. 1. General MTCMOS circuit architecture. 2 J. Low Power Electronics 4, 1–12, 2008 Bailey et al. Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power 3. NULL CONVENTION LOGIC (NCL) 3.1. NCL System Architecture and In1 Dual-Rail Encoding P UN Sleep P0 Inn Quasi delay-insensitive (QDI) design styles, like NULL X1 Convention Logic (NCL), require very little, if any, timing Sleep analysis to ensure correct operation (i.e., they are correct P1 by construction).NCL circuits utilize multi-rail signals, Out such as dual-rail logic, to achieve delay-insensitivity. X2 A dual-rail signal, D, consists of two wires, D0 and D1. The DATA0 state (D0 = 1, D1 = 0) corresponds to a P DN Sleep N0 Boolean logic 0; the DATA1 state (D0 = 0, D1 = 1) corre- sponds to a Boolean