Lars Ohlsson 2018-10-02 F9 – Differential and Multistage Amplifiers Outline Reading Guide Sedra/Smith 7ed int • MOS differential pair • Chapter 8 • Common mode signal operation • Differential mode signal operation • Large signal operation • Small signal operation • Differential and common mode half-circuits Problems Sedra/Smith 7ed int • Common mode rejection • P8.2, 8.8, 8.17(a-b), 8.18, 8.84 • DC offset • Differential amplifier w/ current mirror load • Multistage amplifiers ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 1 Common and Differential Mode Signals (recap) • Two signal sources • 푣1: reference signal minus a (half) component • 푣2: reference signal plus a (half) component • Differential mode signal component, 푣퐼푑 = 푣2 − 푣1 • Typically the “interesting” part of the signal 1 • Common mode signal component, 푣 = 푣 + 푣 퐼푐푚 2 1 2 • Typically a reference or noise level, not desired • Common mode rejection ratio (CMRR) • Differential to common mode power gain ratio, 퐴푑 퐶푀푅푅 = 20 log10 퐴푐푚 Observe the split and polarity of the differential sources. ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 2 MOS Differential Pair • Two balanced transistors • Same technology, 푘푛 • Same threshold, 푉푡푛 • Same size, 푊/퐿 • Arranged symmetrically • Equal load, 푅퐷 • Share one current sink, 퐼 • Source terminals joined, 푉푆 • Equal gate bias, 푉퐺 • Equal overdrive bias, 푉푂푉 = 푉퐺푆 − 푉푡푛 • Differential ports • Input over gates The MOSFETs in the differential pair (and current sink) • Output over drains must be operated in saturation mode. ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 3 Common Mode Operation • Drain level: constant • Forced current through load • Resistance sets voltage drop 푅 퐼 푉 , 푉 = 푉 − 퐷 퐷1 퐷2 퐷퐷 2 • Gate overdrive: constant • Forced current through saturated MOSFETs • Materials and design sets overdrive 1 푊 퐼 퐼 , 퐼 = 푘′ 푉2 = 퐷1 퐷2 2 푛 퐿 푂푉 2 퐼 푉푂푉ቚ 퐼 = • Source level: varies with CM input 퐼 =퐼 = 푊 퐷1 퐷2 2 푘′ • Sink must “absorb” gate voltage offsets 푛 퐿 푉푆 = 푉퐶푀 − 푉퐺푆 = 푉퐶푀 − 푉푡푛 − 푉푂푉 The MOSFETs in the differential pair share one current sink. ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 4 Differential Mode Operation • Difference signal between Q1 and Q2 • Input over gates, 푣푖푑 = 푣퐺1 − 푣퐺2 퐼 • Output over drains, 푣 = 푣 − 푣 푉푂푉ቚ 퐼 = 표푑 퐷2 퐷1 퐼퐷1=퐼퐷2= ′ 푊 2 푘푛 퐿 • Positive(/ negative) differential input • Different overdrive in Q1 and Q2 • Redistribution of current towards Q1(/ Q2) branch of the pair • Limit of operation • Steering all current to one transistor − 2푉푂푉 < 푣푖푑 < 2푉푂푉 ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 5 Large Signal Operation • Gate overdrive level determines 2 differential voltage window 퐼 퐼 푣푖푑 푣푖푑 푖퐷1,2 = 퐼퐷1,2 ± 푖푑 = ± 1 − 2 푉푂푉 2 2푉푂푉 푣 푖 = 푣 ≪ 2푉 ≈ 푔 푖푑 푑 푖푑 푂푉 푚 2 2퐼퐷1,2 퐼 푔푚 = = 푉푂푉 푉푂푉 ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 6 Small Signal Operation • Small signal differential input voltage, 2퐼퐷1,2 퐼 푔푚 = = superimposed on bias point 푉푂푉 푉푂푉 푣 푣 = 푣 − 푣 ≪ 2푉 푣 = 푉 ± 푖푑 푖푑 푔1 푔2 푂푉 퐺1,퐺2 퐶푀 2 푣푖푑 푖푑 = 푖푑1 = −푖푑2 = 푔푚 • Small signal perturbation of current 2 퐼 푣 푣표푑 = 푣푑2 − 푣푑1 = 푔푚푣푖푑푅퐷 푖 = ± 푔 푖푑 퐷1,퐷2 2 푚 2 • Differential voltage developed over drain terminals 퐼 푣 푣 = 푉 − 푅 ± 푔 푖푑 퐷1,퐷2 퐷퐷 퐷 2 푚 2 • Differential gain results 푣표푑 퐴푑 = = 푔푚푅퐷 푣푖푑 ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 7 How does a finite MOSFET output resistance affect the gain expression? 푣표푑 ′ 퐴푑 = = 푔푚푅퐷 푣푖푑 ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 8 (Small Signal Analysis Directly on the Circuit Schematic) • You may save some ink and time… …or make grave mistakes 푣표푑 퐴푑 = = 푔푚 푟표||푅퐷 푣푖푑 Imagine the small signal model and work on the original schematic (experienced users only). ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 9 Differential and Common Mode Half Circuits • Differential mode: Push-pull anti-symmetry • Source output resistance: virtual ground • No differential current flow • Constant bias condition • Load resistance: split • Half the voltage level • Half the impedance value • Common mode: Push-push symmetry • Source output resistance: split • Half the current level • Twice the impedance value • Load resistance ignored • Same voltage on both sides Half circuits are only valid if pair and load are symmetric. ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 10 MOS Differential Pair w/ Active Load • Improved performance as compared to passive load, essentially a differential CS amplifier w/ active load 푣표푑 퐴 = 푔 푅 ||푅 퐴푑 = = 푔푚1 푟표1||푟표3 푑 푚1 표푛 표푝 푣푖푑 ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 11 BREAK ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 12 Common Mode Gain and CMRR • Differential gain, 퐴푑 퐴푑 = 푔푚푅퐷 • Common mode gain, 퐴푐푚 • Arises from mismatch −푅퐷 Δ푅퐷 Δ푔푚 퐴푐푚 = + 2푅푆푆 푅퐷 푔푚 • Common mode rejection ratio (CMRR) • Ratio of differential to common mode gain 퐴 −2푔 푅 퐶푀푅푅 = 푑 = 푚 푆푆 Δ푅 Δ푔 퐴푐푚 퐷 + 푚 푅퐷 푔푚 Device matching and high current source resistance keeps CMRR high. ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 13 DC Offset • Imperfectly balanced pair… • Unequal load, Δ푅퐷 = 푅퐷1 − 푅퐷2 푊 푊 푊 • Unequal size, Δ = − 퐿 퐿 1 퐿 2 • Unequal threshold, Δ푉푡푛 = 푉푡푛1 − 푉푡푛2 • … • Output non-zero at zero input, as current not balanced • Input referred offset voltage, 푉푂푆 • Input that cancels offset 푉 Δ푅 2 푉 Δ 푊Τ퐿 2 푉 | 2 푂푉 퐷 푂푉 2 푂 푉퐼푑=0 푉푂푆 ≈ ෍ 푉푂푆푛 = + + Δ푉푡푛 푉푂푆 = 푛 2 푅퐷 2 푊Τ퐿 퐴푑 ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 14 Differential to Single Ended Conversion? • Option 1: Trash input branch current • A convenient but sub-optimal approach Although successfully converting to single ended, half of the signal current is lost to the supply. ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 15 How to reflect differential pair input branch current to output branch? ? ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 16 MOS Differential Amplifier w/ Current Mirror Load • Option 2: Mirror current to output • Superimposes both branch currents • KCL “magic” at output node • Differential mode currents cleverly forced into load 퐼 퐼 푖 = + 푖 − − 푖 = 2푖 푑 2 푑 2 푑 푑 • Common mode and dc currents must ignore load 퐼 퐼 푖 = + 푖 − + 푖 = 0 퐶푀 2 푐푚 2 푐푚 Current mirror does not load the differential pair symmetrically. ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 17 Differential Amplifier: Short Circuit Transconductance • Identify equivalent transconductance amplifier • Infinite input resistance • Transconductance • Finite output resistance 1 1 퐴 = 퐺 푅 ≈ 푔 푟 = 퐴 푑 푚 표 2 푚 표 2 0 푖푑 퐺푚 = ≈ 푔푚 푣푖푑 ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 18 Differential Amplifier: Output Resistance • Identify equivalent transconductance amplifier • Infinite input resistance • Transconductance • Finite output resistance 1 1 퐴 = 퐺 푅 ≈ 푔 푟 = 퐴 푑 푚 표 2 푚 표 2 0 푣푥 푅표 = ≈ 푟표2||푟표4 푖푥 ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 19 Differential Amplifier: Common Mode Gain and CMRR • Asymmetrical loading 퐴푑 퐶푀푅푅 = ≈ − 푔푚푟표 푔푚푅푆푆 • Diode connected transistor 퐴푐푚 • Common source transistor • Mirror approximately buffers current • Common gate source/ load transformations useful 푣표푑 퐴푑 = = 퐺푚푅표 ≈ 푔푚 푟표2||푟표4 푣푖푑 푣표 −1 퐴푐푚 = = − 1 − 퐴푚 퐺푚푐푚 푅표푚||푅표2 ≈ 푣푖푐푚 2푔푚푅푆푆 ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 20 Multistage Amplifiers • Multistage seen as functional blocks • Noise/ CM rejection • Signal gain (small signal) • Power (linearity) • Differential input and interstage • Differential gain • CM (noise or interference) rejection • Single ended output stages • Gain and power level • Resistance transformation • Single ended output typically Multistage amplifier is co-desiged system, • Load to ground its stages dedicated to specific tasks. ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 21 Two-Stage CMOS Op Amp • Bias current steering circuit • Input stage: differential PMOS pair • Gain and single ended conversion • NMOS current mirror load • Output stage: common source NMOS • Gain w/ active load • Stability • Frequency compensation feedback capacitor • Compact, moderate gain, but rather high output impedance ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 22 Four Stage BJT Op Amp • Bias current steering circuit • Input stage: differential NPN pair • Differential in/ out gain • Second stage: differential NPN pair • Gain and single-ended conversion • Third stage: degenerated common emitter PNP • Gain and level shift • Output stage: emitter follower • Low output impedance • Higher gain, lower output impedance ETIN70 – Modern Electronics: F9 – Differential and Multistage Amplifiers 23.