1 Cache Memory Design with Magnetic Skyrmions in a Long Nanotrack Mei-Chin Chen, Ashish Ranjan, Anand Raghunathan, Fellow, IEEE and Kaushik Roy, Fellow, IEEE School of Electrical and Computer Engineering, Purdue University, West Lafayette, 47906, USA Abstract—Magnetic skyrmion (MS), a vortex-like region with technology, domain wall motion based racetrack memory, was reversed magnetization in nanomagnets, has recently emerged proposed by IBM [1]. In a racetrack memory, multiple data bits as an exciting development in the field of spintronics. It has can be coded in a sequence of magnetic domains, separated a number of beneficial features, including remarkably high stability, ultra-low depinning current density, and extremely by domain walls, within a nanowire. DWM-based caches [2]– compact size. Due to these benefits, skyrmions have generated [5] have shown significant improvement in performance (with great interest in the design of spintronic memory. In this work, higher packing density and better energy efficiency) over other we evaluate the use of skyrmion-based memory as a last-level spintronic memory devices. However, the motion of domain cache for general purpose processors. In the skyrmion-based walls might be pinned by the presence of defects [6], raising memory structure, data can be densely packed as multiple bits in a long magnetic nanotrack. Write operations are performed concerns about the feasibility of DWM-based memory. by injecting a spin-polarized current in the nanotrack. Since Magnetic skyrmions have recently emerged as a promising multiple skyrmions (each representing a bit) are packed into a alternative for future memories [7]–[10]. They can be observed single nanotrack, they need to be accessed by shifting them along in non-centrosymmetric bulk magnetic materials or ultra- the nanotrack with a charge current passing through a spin-Hall thin magnetic systems with breaking inversion symmetry and metal (SHM). We identify the following key challenges associated with MS-based cache design: (i) the high current requirements large spin orbital coupling. The state of a magnetic skyrmion for skyrmion nucleation limits the density benefits offered by can be explained by the presence of Dzyaloshinskii-Moriya these structures, since the transistor supplying write currents Interaction (DMI) [11], [12] – the DMI between two atomic is the limiting factor that determines the bit-cell area; (ii) the spins S1 and S2 with a neighboring atom can be expressed as proposed nanotrack structure results in significant performance H = −D1 2 · (S1 × S2) where D1 2 is the Dzyaloshinskii- overheads due to the latency arising from the shift operations; DM , , (iii) the skyrmions move toward the edge of the nanotrack Moriya (DM) vector [7], [8], [13]–[16]. Magnetic skyrmions during shift operations owing to the Magnus force. Hence, an have been shown to possess several benefits over domain wall additional idle operation time is required to relax skyrmions back motion based racetrack memory in terms of stability, density, through repulsive force from the edge; (iv) to avoid annihilation and are less limited by imperfectness of the material. Specifi- of skyrmions from the edge, the duration and the current density cally, topological properties prevent the motion of skyrmions of the shift operation have to be well controlled. To overcome these challenges, a multi-bit skyrmion cell with appropriate from being pinned at defect sites in a magnetic layer, and thus peripheral circuit is proposed, considering the heterogeneity in skyrmions are more robust information carriers. the read/write characteristics. The density benefits are explored Magnetic skyrmions (MS) can be stored as multiple bits in by performing layout of different multi-bit cells. We perform a a long nanotrack to realize highly dense memory. Ref. [17] systematic device-circuit-architecture co-design to evaluate the first demonstrated the use of magnetic skyrmions to realize feasibility of our proposal. Our experiments demonstrate the potential of, and the challenges involved in, using skyrmion-based on-chip caches. The work proposed the use of a shift-based memory as last-level caches. write mechanism [18] for creation of skyrmions. However, such an approach is considered to be applicable for domain Index Terms—Magnetic Skyrmion (MS), Spin-Hall metal (SHM), Magnus force, Dzyaloshinskii-Moriya Interaction (DMI) wall motion based device. No experimental (or simulation) results to date have demonstrated the creation of skyrmions using the shift-based mechanism. In our work, a magnetic skyrmion is written (or nucleated) by injecting a local spin- I. INTRODUCTION polarized current in the nanotrack, whereas the read operation NCREASED leakage current and process variations are is performed by sensing the change in resistance arising from I a major challenge to memories realized using deeply- the presence (or absence) of skyrmion at a specific location scaled CMOS devices. The need for non-volatility (zero off- in the nanotrack. In order to read or write a bit stored in the state leakage), higher density, and robustness has consequently nanotrack, a variable number of shift operations are required led researchers to explore alternative technologies to replace depending on the location relative to the read/write port. The traditional CMOS-based on-chip memories. Several emerging noticeably high density and non-volatility offered by MS- technologies such as phase change memory (PCM), resistive based memory are key positives for last level on-chip cache random-access memory (RRAM), spin-transfer torque Mag- applications. netic RAM (STT-MRAM), and domain wall motion (DWM) We explore the use of magnetic skyrmions as last-level based memory have been proposed as potential substitutes for on-chip caches in general purpose processors. We propose SRAM and DRAM. One such promising high-density memory a multi-port skyrmion-based cell and evaluate its potential Digital Object Identifier: 10.1109/TMAG.2019.2909188 1941-0069 c 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information. 2 in realizing an on-chip memory array. Despite possessing a number of beneficial attributes such as high stability, non- volatility, high density1, and low leakage, magnetic skyrmions pose certain challenges: (i) the current density required for skyrmion nucleation [19] is substantially higher, necessitating the need for large access transistors for writing a skyrmion, in turn limiting the density benefits. (ii) the variable access latency arising from packing multiple bits in a single nan- otrack, leads to energy and performance overheads. (iii) the motion of skyrmions drifts away from the direction of electron flow owing to the Magnus force [20]. In order to relax the skyrmions back to the center region of the nanotrack, an Fig. 1: Schematic of MS-based device and bit-cell. The pro- idle operation time is needed which leads to additional shift posed device structure can perform read/write/shift operations. latency. (iv) skyrmions might suffer annihilation through the A skyrmion can be nucleated in the nanotrack (yellow layer) edges due to large drive current density required for high- by injecting a spin-polarized current through the left MTJ. speed operation. To address these challenges, we perform a The motion of skyrmions can be driven by utilizing vertical design-space exploration for the multi-bit skyrmion cell while injection of a spin current generated from a charge current considering the peripheral circuits required to perform these flowing through the Spin-Hall Metal (SHM) layer (blue layer). operations. We also performed layout to estimate the density The reference MTJ is used to form a voltage divider on the benefits of the proposed multi-bit cell. To keep skyrmions read port, and the presence of a skyrmion can be detected by enclosed in the nanotrack under high current injection, it is es- sensing the voltage at the output of the inverter. sential to analyze the various design choices possible and their impacts on system energy and performance. We developed a device-circuit-architecture framework to understand these operation. In the following paragraphs we describe these design points for the proposed multi-bit cell. operations in detail along with the peripheral circuits required The key contributions of this work are as follows: to perform these operations • We explore the feasibility of last-level cache design Nucleation of a skyrmion (Write operation). A skyrmion for general purpose processors with magnetic skyrmion- is nucleated in the nanotrack by injecting a local spin- based memory. polarized current through the MTJ on the left (write MTJ). • We propose a magnetic skyrmion-based multi-bit cell and This is performed by charging the bitline (BL) to VWRITE, utilize suitable circuit and architecture optimizations that sourceline (SL) to ground (GND), and turning ON the write mitigate the unique challenges posed by the skyrmion access transistors by driving the write wordlines (WWL) structure. to VDD. Nucleating a skyrmion requires that the injected • We develop a systematic device-to-architecture co-design spin-polarized current exceeds certain threshold Jth [19]. We framework and perform an in-depth analysis of the den- exploit spin-polarized current generated from the electrical sity benefits, along with the energy and performance current through a 20 nm-diameter write MTJ to create a trade-offs associated with the proposed skyrmion-based skyrmion. The proposed device structure consists of a 0.4 nm- cache. Our experiments on the PARSEC benchmark suite thick ferromagnetic nanotrack adjacent to a 3 nm-thick SHM. [21] demonstrate 2.41× improvement in cache energy The material parameters used in our simulations correspond with 2% average degradation in cache performance over to Co/Pt multilayers [19], and are shown in Table IV. In our an iso-area traditional SRAM-based L2 cache. simulation, a stable skyrmion can be nucleated in a 60 nm The rest of this paper is organized as follows.