The Design and Implementation of the Nintendo Entertainment System Jonathan Downey Lauri Kauppila Brian Myhre 6.111 Introductory Digital Systems Laboratory Professor Chris Terman December 9, 2004 Abstract Two decades ago the Nintendo Entertainment System entered the US market and continues to profoundly influence and define American culture and consumer electronics. For the final project in Introductory Digital Systems Laboratory, our team decided to design and construct the console to its original specifications. The system is composed of two major subsystems, the Central Processing Unit (CPU) and Picture Processing Unit (PPU), and we divided up tasks along the lines of these major functional components. The project began with extensive research into the technical specifications and design. From there we implemented the system on three FPGAs, one for the CPU, one for the Picture Processing, and one for the VGA Output Generation, using the Verilog hardware description language. In the end, the various components were not fully integrated into a complete console, but we achieved all our major system design goals and are very close to a working Nintendo Entertainment System. Downey – Kauppila – Myhre 6.111 Final Project Report Table of Contents Title..................................................................................................................Page Project Motivation................................................................................................... 4 Background............................................................................................................ 4 Project Overview .................................................................................................... 5 Overall Nintendo System Architecture....................................................................... 6 The Central Processing Unit..................................................................................... 8 The Historic 6502 ....................................................................................................................... 8 System Hardware........................................................................................................................ 8 Bus Architecture ..................................................................................................................... 8 Instruction Set ......................................................................................................................... 9 Addressing Modes ................................................................................................................ 10 Interrupts............................................................................................................................... 10 Implementation ......................................................................................................................... 11 Added Features to the CPU.................................................................................... 18 Boot Mode ................................................................................................................................ 18 Custom Output Registers .......................................................................................................... 18 Custom Timer Register............................................................................................................. 18 Demonstration: The 6502 in Action ........................................................................ 19 Hardware Setup: Scanning LEDs on the Output Port............................................................... 19 Gameplay: Super Steal’em Tic-Tac-Toe .................................................................................. 19 Nintendo Picture Processing Unit............................................................................ 20 Registers.................................................................................................................................... 21 Graphics Rendering .................................................................................................................. 22 I/O control................................................................................................................................. 23 Internal Memory ....................................................................................................................... 24 VGA Output Module .............................................................................................. 24 Sprite Rendering................................................................................................... 25 Overview .................................................................................................................................. 25 Rendering stages ....................................................................................................................... 27 Range Evaluation...................................................................................................................... 27 Memory Fetch........................................................................................................................... 29 Real-time Output....................................................................................................................... 31 Background Rendering .......................................................................................... 31 Background Rendering .......................................................................................... 32 Overview................................................................................................................................... 32 Memory Fetch Cycle................................................................................................................. 32 Cycle One: The Name Table................................................................................................. 35 Cycle Two: The Attribute Table........................................................................................... 35 Cycle Three: The Pattern Table Lower Bit........................................................................... 36 Cycle Four: The Pattern Table Upper Bit............................................................................. 37 Real-Time Output ..................................................................................................................... 38 Testing and Debugging ......................................................................................... 39 Conclusion ........................................................................................................... 41 Page 1 Downey – Kauppila – Myhre 6.111 Final Project Report Table of Contents (cont…) Title..................................................................................................................Page Appendix A: Control Signals for Clock Cycle Zero..................................................... 42 Appendix B: Control Signals................................................................................... 44 Appendix C: 6502 Instruction Clock Cycles.............................................................. 47 Appendix D: CPU Verilog ....................................................................................... 49 addr_mod_decode.v.................................................................................................................. 49 ALU.v ....................................................................................................................................... 51 Clock_Generator.v.................................................................................................................... 52 CPU.v........................................................................................................................................ 54 Instr_Decode.v.......................................................................................................................... 86 Interrupt_Control.v ................................................................................................................... 90 NES_CPU.v .............................................................................................................................. 91 Reset.v....................................................................................................................................... 94 Timing_Control.v...................................................................................................................... 95 Appendix E: PPU Verilog........................................................................................ 96 ppu.v.......................................................................................................................................... 96 table2vga.v.............................................................................................................................. 106 ppu_sprite_renderer.v ............................................................................................................. 108 ppu_sprite_buffer.v................................................................................................................. 116 ppu_background_renderer.v ................................................................................................... 118 ppu_test_controller.v .............................................................................................................