TMS320DM644x DMSoC Video Processing Front End (VPFE) User's Guide Literature Number: SPRUE38H August 2010 2 SPRUE38H–August 2010 Copyright © 2010, Texas Instruments Incorporated Preface ...................................................................................................................................... 13 1 Introduction ...................................................................................................................... 15 1.1 Purpose of the Video Processing Front End ....................................................................... 15 1.2 Features ................................................................................................................. 16 1.3 Functional Block Diagram ............................................................................................. 20 1.4 Use Case Statement .................................................................................................. 20 2 Camera Subsystem Environment ........................................................................................ 21 2.1 Parallel Generic Configuration (Raw) ............................................................................... 22 2.2 ITU-R BT.656 Configuration Functional Interface ................................................................. 24 2.3 Generic YUV Interface ................................................................................................ 27 2.4 VPFE/Camera Subsystem I/O Multiplexing ........................................................................ 28 3 Integration ........................................................................................................................ 29 3.1 Clocking, Reset and Power Management Scheme ............................................................... 29 3.2 Hardware Requests ................................................................................................... 30 3.3 VPFE Top-Level Register Mapping Summary ..................................................................... 31 4 Functional Description ....................................................................................................... 32 4.1 Block Diagram .......................................................................................................... 32 4.2 Interfacing with Image Sensors ...................................................................................... 33 4.3 VPFE Data/Image Processing ....................................................................................... 37 4.4 VPFE Arbitration and Data Transfer ................................................................................. 78 4.5 Error Reporting ......................................................................................................... 82 5 Programming Model .......................................................................................................... 83 5.1 Setup for Typical Configuration ...................................................................................... 83 5.2 Resetting the Camera Subsystem ................................................................................... 83 5.3 Configuring the Clocks and the Control Signals ................................................................... 83 5.4 Programming the CCD Controller ................................................................................... 84 5.5 Programming the Preview Engine ................................................................................... 91 5.6 Programming the Resizer ............................................................................................. 96 5.7 Programming the H3A ............................................................................................... 100 5.8 Programming the Histogram ........................................................................................ 103 5.9 Programming the Shared Buffer Logic (VPSS Registers) ...................................................... 106 5.10 Error Identification .................................................................................................... 107 5.11 Supported Use Cases ............................................................................................... 107 6 Video Processing Front End (VPFE) Registers .................................................................... 120 6.1 CCD Controller (CCDC) Registers ................................................................................. 120 6.2 Preview Engine (PREV) Registers ................................................................................. 144 6.3 Resizer Registers ..................................................................................................... 166 6.4 Histogram Registers ................................................................................................. 175 6.5 Hardware 3A (H3A) Registers ...................................................................................... 184 7 Video Processing Subsystem (VPSS) Registers .................................................................. 198 7.1 VPSS Peripheral Revision and Class Information Register (PID) ............................................. 198 SPRUE38H–August 2010 Table of Contents 3 Copyright © 2010, Texas Instruments Incorporated www.ti.com 7.2 VPSS Peripheral Control Register (PCR) ......................................................................... 199 7.3 SDRAM Non-Real-Time Read Request Expand Register (SDR_REQ_EXP) ................................ 200 Appendix A Revision History ..................................................................................................... 201 4 Contents SPRUE38H–August 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com List of Figures 1 Video Processing Subsystem (VPSS) Block Diagram................................................................ 15 2 Video Processing Front End (VPFE) Block Diagram ................................................................. 20 3 Raw Mode Timing Diagram .............................................................................................. 23 4 DDR2 Output Format ..................................................................................................... 23 5 BT.656 Signal Interface................................................................................................... 25 6 BT.656 Mode Data Format in SDRAM ................................................................................. 26 7 Video Processing Subsystem Block Diagram ......................................................................... 32 8 CCD Controller Frame and Control Signal Definitions ............................................................... 34 9 CCD Controller Processing Block Diagram – Raw Data Mode ..................................................... 37 10 CCD Controller Color Patterns .......................................................................................... 37 11 CCD Controller Input Sampling Block Diagram – Raw Data Mode................................................. 38 12 CCD Controller Initial Processing Block Diagram – Raw Data Mode .............................................. 39 13 CCD Controller Optical Black Averaging and Application............................................................ 40 14 CCD Controller Video Port Interface and Data Formatter Block Diagram – Raw Data Mode................... 42 15 CCD Controller Data Formatter Conversion Area Selection......................................................... 43 16 CCD Controller Video Port Framing .................................................................................... 43 17 CCD Controller Output Formatter Block Diagram – Raw Data Mode .............................................. 44 18 Example for Decimation Pattern......................................................................................... 45 19 A-Law Table................................................................................................................ 46 20 Frame Image Format Conversion (de-interlaced, 2-field input) ..................................................... 49 21 Example Formats of Input and Output Image ......................................................................... 50 22 DDR2 Output Format ..................................................................................................... 51 23 CCD Controller Processing Block Diagram – YUV Modes .......................................................... 51 24 CCD Controller Input Sampling Block Diagram – YUV Modes...................................................... 52 25 CCD Controller Initial Processing Block Diagram – YUV Modes ................................................... 53 26 CCD Controller Video Port Interface and Data Formatter Block Diagram – YUV Modes........................ 54 27 CCD Controller Output Formatter Block Diagram – YUV Modes ................................................... 54 28 Preview Engine Processing Flow Block Diagram ..................................................................... 56 29 Horizontal Distance for Bayer Pattern input............................................................................ 57 30 Black Adjustment Functional Model..................................................................................... 58 31 Gamma Table Example................................................................................................... 59 32