AN-543 a APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 DSP and the AD9850 Direct Digital Synthesizer by Dean R. Becker The following describes the implementation of a high Recent developments in digital signal processing (DSP) quality all-digital FM RF generator for use with audio fre- devices have made it possible to create high quality FM quency input signals. The FM RF signal output is in the modulation using all-digital circuitry. This modulator broadcast FM band and can be monaural or stereo. does not require periodic recalibration, it does not drift with temperature or power supply variations, and it is FM modulators have been with us since the time of very easy to reproduce since there are no analog adjust- Major Edwin H. Armstrong (sometimes known as the ments (other than the level of the input analog modulat- father of FM) and his classic 1936 paper on the subject. ing signal). At the heart of this circuit is a Direct Digital He first put down on paper the fundamental concept of a Synthesizer (DDS), such as the AD9850 Complete-DDS fixed center frequency that is varied per a constant de- (C-DDS) device. The AD9850 consists of a digital phase viation ratio that is independent of the frequency of the accumulator, a phase/amplitude converter and a D/A modulating signal. FM became very popular because converter. It creates a linear ramp in the phase accumu- much of the noise generated in nature exhibits AM char- lator with a frequency that is dependent on the phase acteristics. The signal-to-noise ratio of an FM signal will accumulator’s input value. The ramp is mapped to a be found to exceed that of an AM signal due to the im- sampled sinusoidal signal by the phase-to-amplitude provement ratio related to the deviation ratio. We are all converter. The sampled digital signal is then D/A con- familiar with the wideband FM broadcast band and its verted and filtered with a reconstruction filter to pro- superior sound quality and noise immunity when com- duce an analog waveform. All functions of the DDS pared with AM broadcast. (except the analog reconstruction filter) are contained in Analog FM modulators typically employ an oscillator the AD9850 chip. The sampled signal is created at a with a varactor diode in the tuned circuit. The voltage to sample rate of 125 MHz, allowing high frequency RF out- the varactor is varied by the modulating signal, which put. Prior to the release of the AD9850, very fast, inex- changes its capacitance, therefore changing the reso- pensive C-DDS devices did not exist. For a more detailed nant point of the oscillator’s tuned circuit, which shifts explanation of the operation and specifications of a the frequency. As noted above, constant center fre- C-DDS device, please refer to the theory of operation in quency and deviation ratio are essential to quality FM. the AD9850 data sheet. Much work has been done to embellish the basic oscilla- tor circuit to provide the needed stability. Even though HARDWARE IMPLEMENTATION complex circuitry can be added to automatically com- The implementation of the FM RF generator consists of pensate for power supply and temperature variations, an Analog Devices EZ-KIT Lite 16-bit DSP development these circuits still require periodic recalibration to deal board, some I/O decode circuitry, and an evaluation with component aging. board for the DDS—the AD9850-FSPCB as shown in Figure 1. LINE IN AD9850/FSPCB AUDIO IN EZ-KIT LITE L AND R DDS AD9850 AD1847 FM RF ADSP-2181 I/O DECODE 8-BIT STEREO ADSP-2181 OUTPUT ␮ BUS LOGIC DATA CODEC DSP P DAC 125MHz OUT XOSC Figure 1. Block Diagram of FM RF Generator Implementation AN-543 AD9850-FSPCB EVAL BOARD EZ-KIT LITE MODIFIED CONNECTIONS BOARD 2 19 D7 D15 D1 Q1 P2-30 3 18 D6 D14 D2 Q2 P2-29 4 17 D5 D13 D3 Q3 P2-28 5 16 D4 D12 D4 Q4 P2-27 6 U2 15 D3 D11 D5 Q5 P2-26 7 14 D2 D10 D6 Q6 P2-25 8 13 D1 D9 D7 Q7 P2-24 9 12 D0 D8 D8 Q8 P2-23 11 CLK 1 OE 74AC574 CONNECT DIRECTLY TO 74AC574 PINS I/O INTERFACE BOARD 2 19 D1 Q1 43IOMS 3 18 U2B J2-41 D2 Q2 4 17 1 D3 Q3 12 2 74LS04 U1A 5 16 13 A1 D4 Q4 J2-2 6 U3 15 D5 Q5 74LS10 65WR 7 14 FQ UD U2C J2-39 D6 Q6 3 8 13 W CLK 6 4 U1B D7 Q7 5 74LS04 A0 9 12 RESET J2-1 D8 Q8 11 74LS10 CLK 1 VCC OE 2 1 RESET U2A J3-37 74AC574 CUT OE's FROM GND 74LS04 THEN TIE TO VCC Figure 2. Schematic of I/O Decode Logic and Interconnections The EZ-KIT Lite contains an Analog Devices ADSP-2181 DSP FIRMWARE IMPLEMENTATION KS-133 16-bit DSP with 16K × 24 of program memory Two programs are described here. The first is for a mon- RAM and 16K × 16 of data memory RAM. aural FM modulator (fm_xmit.dsp) and the second is for stereo (fmStereo.dsp). Both programs are stand-alone Hardware documentation comes with the EZ-KIT Lite single modules and can be loaded into the EZ-KIT Lite development board and schematics for the AD9850 via the serial port using the EZ-KIT Lite monitor. They C-DDS are in the AD9850 data sheet. The I/O decode begin with codec variable initialization. The only differ- logic and interconnections are shown in the schematic ence here is that the codec sample rate for fm_xmit is in Figure 2. 48 kHz while it is set to 44.1 kHz in FmStereo. (This will The AD9850-FSPCB evaluation board is made to inter- be explained with the FmStereo program). This part, the face to the parallel port of a PC. It has a Centronics-type initialization code, interrupt vectors and DSP and codec connector on it and buffers to work with the parallel initialization, was copied from a sample program that port. A simple way to connect it to an external DSP is by comes with the EZ-KIT Lite. The following partial listing disabling the buffers as shown in the schematic, by dis- in Figure 3 describes what happens on every input connecting the output enables from the ground plane of sample from the codec. First the left and right input the PCB and wiring them to VCC. With the buffers dis- samples are divided by two to ensure that they do not abled, the ADSP-2181 on the EZ-KIT Lite can drive the overflow as they are summed together. Next, a devia- AD9850 data lines directly. The I/O interface in the sche- tion value is multiplied by the previous sum and then matic decodes I/O address 1 to create the W_CLK (write has a center frequency value added to the product. This clock) signal and I/O address 2 to create the FQ_UD (fre- is all done in 32-bit double precision to preserve the ac- quency update) signal. These are control signals used to curacy of the C-DDS. Finally, the 32-bit frequency word write the consecutive frequency bytes into the AD9850 is broken into four bytes and sent to the AD9850 C-DDS. and then strobe the entire 32-bit frequency word into the operational register respectively. RESET is brought in to initialize the AD9850. Please refer to the AD9850 data sheet for more information on loading the C-DDS. –2– AN-543 .const w_clk= 0x0001; { 9850 write clock address } mr1 = mr2; .const fq_ud= 0x0002; { 9850 frequency update address } mr = mr + mx1 * my1 (ss); { mpy MSWs and add previous product } ax1 = 0x4710; { MSW of DDS center frequency } input_samples: ax0 = 0xcb29; { LSW of DDS center frequency } ena sec_reg; { use shadow register bank } ay1 = mr1; { MSW of modulated deviation } mr0 = dm (rx_buf + 1); { Left data in } ay0 = mr0; { LSW of modulated deviation } mr1 = dm (rx_buf + 2); { Right data in } ar = ax0 +ay0; { add LSWs first } { loopback inputs to outputs } mr0 = ar, ar=ax1 + ay1 + c; { save result LSW and get sum of MSWs } sr = ashift mr0 by -1 (hi); { scale left input by 0.5 } af = pass sr1; { setup for add } sr0 = 0; { DDS phase number = 0 } sr = ashift mr1 by -1 (hi); { scale right input by 0.5 } io(w_clk) = sr0; { output first byte to DDS } ar = sr1 + af; { add left and right together } sr = lshift ar by -8 (hi); { move MSB of MSW to align with D8-D15 } io(w_clk) = sr1; { output second byte to DDS, MSB of MSW } dm (tx_buf + 1) = ar; { Left data out } nop; dm (tx_buf + 2) = ar; { Right data out } io(w_clk) = ar; { output third byte to DDS, LSB of MSW } { same output on both channels } sr = lshift mr0 by -8 (hi); { move MSB of LSW to align with D8-D15 } io(w_clk) = sr1; { output forth byte to DDS, MSB of LSW } mx1 = 0x004e; { MSW of peak deviation value } nop; mx0 = 0xa4a8; { LSW of peak deviation value } io(w_clk) = mr0; { output fifth byte to DDS, LSB of LSW } my1 = ar; { L+R codec value (MSW only, LSW=0) } nop; { 32 bit mpy with one of the LSWs=0 } io(fq_ud) = sr0; { output latch pulse, data is irrelevant } mr = mx0 * my1 (us); { codec MSW * deviation LSW } mr0 = mr1; { shift right by 16 to align with next } rti; Figure 3.