PCI-X & PCI Core User's Guide Version 7.1.0 27-Feb-2007 © PLD Applications, 1996-2007 PLD Applications Web: http://www.plda.com Europarc Pichaury A2 Email: [email protected] 1330, rue Guillibert USA : 1 866 513 0362 (toll free) 13856 Aix-en-Provence Intl : + 33 442 393 600 CEDEX 3 - France Fax : + 33 442 394 902 Associate Member PCI-X & PCI Core User's Guide Features General ° 32-bit/64-bit PCI-X & PCI master/target interface ° Supports bus speed up to 133 MHz ° Multi-function core can implement up to 2 independent functions ° Full support for 64-bit addressing ° PCI-X Specification 2.0a mode 1 compliant ° PCI Specification 3.0 compliant ° Supports PCI power management ° Built-in support for in-site programming through JTAG interface ° Supports Message Signalled Interrupts Customization ° Easy customization with the PCI Wizard's user interface and on-line help. ° PCI Wizard has built-in support for VHDL and Verilog. ° All features can be parameterized, removing all unused logic ° Full plug-and-play support Configuration ° Supports all required and optional type 0 configuration registers ° Up to 6 BARs plus expansion ROM can be implemented ° Up to 32 user defined configuration registers Data transfer ° Supports up to 4KB burst transfers with zero wait-state insertion. ° Supports all memory and I/O commands ° Supports interrupt acknowledge cycles in target mode ° Can insert wait-states and generate all types of terminations ° Up to two split channels and 32 outstanding split transactions DMA ° Up to 4 independent DMA channels with rotating priority ° Flexible backend interface can directly control FIFO devices. ° Can generate all existing bus commands ° Optional scatter-gather support ° 64-bits data transactions are dynamically negotiated ° Split is fully supported on all DMA channels Design files ° Standard VHDL and Verilog source code for ASIC design and simulation ° Highly optimized encrypted VHDL code for Altera & Xilinx FPGAs 2 PCI-X & PCI Core User's Guide Table of Contents PREFACE.............................................................................................................................................................. 4 1 – PCI-X & PCI CORE BASICS ....................................................................................................................... 5 1.1. GENERAL ARCHITECTURE................................................................................................................................................. 5 1.2. PARITY CONTROL............................................................................................................................................................. 6 1.3. TARGET STATE-MACHINE ................................................................................................................................................ 7 1.4. DATA PATH...................................................................................................................................................................... 9 1.5. CONFIGURATION SPACE.................................................................................................................................................. 10 1.6. MULTIPLE FUNCTIONS.................................................................................................................................................... 12 2 - TARGET MODE........................................................................................................................................... 13 2.1. ADDRESS DECODING ...................................................................................................................................................... 13 2.2. TARGET DATA PATH ...................................................................................................................................................... 14 2.3. TRANSACTION PROCESSING ............................................................................................................................................ 15 2.4. CONFIGURATION ACCESSES............................................................................................................................................. 19 2.5. TARGET INTERFACE DESCRIPTION .................................................................................................................................. 20 3 - MASTER MODE........................................................................................................................................... 22 3.1. DMA MODES................................................................................................................................................................. 22 3.2. DYNAMIC TRANSACTION NEGOTIATION........................................................................................................................... 24 3.3. TRANSACTION ALIGNMENT ............................................................................................................................................ 24 3.4. DMA CHANNEL ............................................................................................................................................................. 25 3.5. DMA DATA PATH .......................................................................................................................................................... 29 3.6. DMA INTERFACE DESCRIPTION...................................................................................................................................... 32 4 – SPLIT PROCESSING .................................................................................................................................. 34 4.1. GENERAL DESCRIPTION .................................................................................................................................................. 34 4.2. REQUESTING SPLIT TERMINATION .................................................................................................................................. 35 4.3. SPLIT CHANNELS ............................................................................................................................................................ 36 4.5. SPLIT INTERFACE SIGNALS .............................................................................................................................................. 37 5 - CORE EXTENSIONS................................................................................................................................... 39 5.1. INTERRUPT SUPPORT & MSI........................................................................................................................................... 39 5.2. PLDA PCI-X BOARD INTERFACE.................................................................................................................................... 39 5.3. PLDA CORE STATUS REGISTER & JTAG INTERFACE....................................................................................................... 40 5.4. POWER MANAGEMENT ................................................................................................................................................... 41 5.5. COMPACTPCI HOTSWAP................................................................................................................................................. 43 5.6. CARDBUS ....................................................................................................................................................................... 44 5.7. CORE EXTENSIONS INTERFACE DESCRIPTION .................................................................................................................. 47 APPENDIXES..................................................................................................................................................... 49 A1. REFERENCE DOCUMENTS................................................................................................................................................ 49 A2. PCI-X TERMINOLOGY .................................................................................................................................................... 50 A3. ILLUSTRATION INDEX ..................................................................................................................................................... 51 3 PCI-X & PCI Core User's Guide Preface Introduction © This document is the primary reference and technical manual for PLD Applications PCI-X & PCI core. This manual serves as a guide to incorporate PLD Applications PCI-X & PCI core into designs, for implementation in ASIC or in programmable logic devices. Required Knowledge © In order to take advantage of PCI-X & PCI core features, designers should have a basic understanding of PCI bus architecture and operations. Users can refer to "PCI Bus Fundamentals" document, for an introduction to PCI. Organization © This technical manual contains the following sections : - Section 1, "PCI-X & PCI Core Basics", presents the general architecture of the core and details target-mode functions. - Section 2, "Target Mode", provides many examples depicting target-mode operations. - Section 3, "Master Mode", describes master-mode operations - Section 4, "Split processing", details how to use split transactions - Section 5, "Core Extensions", details features that are extensions to the PCI-X specifications. 4 PCI-X & PCI Core User's Guide 1 – PCI-X & PCI Core Basics This document