CoreConnect™ - A Simplistic Overview PowerPC 405 • 5-stage data path pipeline I-Side On-Chip Memory (OCM) • 16KB D and I Caches • Embedded Memory Management Unit I-Cache Fe tc h & • Execution Unit (16KB) Decode Timers – Multiply / divide unit and MMU Debug – 32 x 32-bit GPR (64 Entry TLB) Logic • Dedicated on-chip memory interfaces D-Cache Execution Unit JTAG • Timers: PIT, FIT, Watchdog (16KB) (32x32 GPR, ALU, MAC) Instruction Trace • Debug and trace support Processor Local Bus Local Processor (PLB) • Performance: D-Side On-Chip – 450 DMIPS at 300 MHz Memory (OCM) – 0.9mW/MHz Typical Power 2 CoreConnect™ Bus Architecture Device Control Register Bus (DCR) • 32-bit bus for initiating peripherals DCR DCR High-Speed • Saves PLB and OPB bandwidth MemoryMemory High-Speed Peripheral ControllerController Peripheral Processor Local Bus (PLB) • 32-bit address, 64-bit data PLBPLB PLBPLB PPC • Primary high-bandwidth bus inter- PPC ArbiterArbiter facing “directly” with the processor 405405 PLB-OPBPLB-OPB Low-Speed Bridge Low-Speed On-chip Peripheral Bus (OPB) Bridge PeripheralPeripheral • 32-bit address, 32-bit data OPBOPB • Lower bandwidth bus interfacing to OPBOPB system peripherals ArbiteArbite r r I/O Interfaces Hard-IP I/O Interfaces Soft-IP CoreConnect Foundation for PowerPC and MicroBlaze 3 CoreConnect™ Example Dedicated Hard IP Flexible Soft IP PowerPC DCR Bus 405 Core Instruction Data PLB OPB Arbiter Bus Processor Local Bus Bridge On-Chip Peripheral Bus Arbiter e.g. Hi-Speed Memory Hi-Speed On-Chip On-Chip On-Chip Peripheral Controller Peripheral Peripheral Peripheral Peripheral ZBTZBT SSRAMSSRAM • Full System Customization Off-Chip DDRDDR SDRAMSDRAM Memory SDRAMSDRAM • High Performance 4 Processor Use Models Dedicated Hard IP Flexible Soft IP BRAM PowerPC DCR Bus 405 Core Instruction Data Data Path Arbiter Data PLB OPB Control Bus PowerPC Processor Local Bus Bridge On-Chip Peripheral Bus 405 Processing Arbiter Path e.g. Hi-Speed Memory Hi-Spe ed On-Chip On-Chip On-Chip Peripheral Controller Peripheral Peripheral Peripheral Peripheral BRAM FP GA Fa br ic ZBZBT T SSRAM Off-Chip DDR SDRAMSDR AM Memory SDRAMSDRAM Buried Processor Embedded Computing • Processor runs from BRAM only • Processor runs from large external • No external pins, no RTOS, no memory peripherals • CoreConnect bus structure, • Typical use: peripherals packet processing, • Typical use: running embedded control functions software applications on RTOS 5 System Diagram Machine Status Reg r31 Register Instruction Instruction Bus Controller File Data Side side Program Data Controller Bus 32 x 32bit LMB LMB Counter r1 Control Unit r0 Instruction Shift / Add / MultiplMultip Logical Subtract Multiply Buffer lyy Processor TM TM CoreConnect Interrupt UART CoreConnect OPB I/F Controller OPB I/F Off-Chip Watchdog General Time r / Off-Chip Memory Time r Purpose I/O Counters Memory 0-4GB 0-4GB Peripherals 6 MicroBlaze & CoreConnect™ • MicroBlaze uses the On-Chip Peripheral Bus from IBM’s CoreConnect bus structure. • All OPB IP is portable between processors • Seamlessly integrate both Hard and Soft processors in Virtex-II Pro 7 Example - CoreConnect™ Based System SRAM/ROM External Peripheral Bus Master Controller Controller I2C UART USB GPIO OPB On-chip Peripheral Bus (OPB) 32-bit FP U Arbite r PPC405 DMA CPU Interrupt OPB MAL 10/100 Ethernet Inst Data Controller Bridge Controller Device Control PLB Register Arbiter Processor Local Bus (PLB) 64-bit Bus Reset PC133/DDR133 PCI-X SRAM Custom Clock Control SDRAM Controller Bridge Controller Logic Power Mgmt SRAM 8 CoreConnect™ Details • Provides three buses for interconnecting cores, library macros, and custom logic: – Processor Local Bus (PLB) – On-Chip Peripheral Bus (OPB) – Device Control Register (DCR) Bus • Shares many similarities with the AMBA 2.0 • IBM offers a no-fee, royalty-free CoreConnect architectural license – Licensees receive the PLB arbiter, OPB arbiter and PLB/OPB bridge designs along with bus model toolkits and bus functional compilers for the PLB, OPB and DCR buses 9 Processor Local Bus (PLB) • High performance, synchronous on chip bus – 32-bit address, 64-bit write and 64-bit read data bus – Instruction Cache Unit PLB master is read only! • Read/write transfers between master and slave devices • Each PLB master has separate address, read data, write data, and transfer qualifiers • PLB slaves have shared, but decoupled, address, read data, write data, transfer qualifiers, and status signals • Access granted through a central arbitration mechanism 10 PLB Block Diagram 11 PLB Features • Architecture supports 8 PLB masters – Instruction Cache and Data Cache are PLB masters • Timing is provided by a single, shared clock source • Overlap read & write transfers permits 2 transfers/clock • Four levels of request priority for each master • Byte enables for unaligned halfword and 3-byte transfers • Support for 16-, 32- and 64-bit line data transfers • Variable or fixed length burst transfers supported 12 PLB Transfer Protocol Address Cycles Request Transfer Address Phase Phase Acknowledge Phase Data Cycles Transfer Data Phase Acknowledge Phase(s) • Decoupled address, read data, and write data bus – Supports overlapped transfers – Address cycle overlapped with read or write data – Read data overlapped with write data • Address pipelining enables next address transfer to begin before current data transfer has completed • Address pipelining & overlapped transfers reduce bus latency 13 Overlapped PLB Transfers 14 On-Chip Peripheral Bus (OPB) • Architected to alleviate system performance bottlenecks by reducing capacitive loading on the PLB – Fully synchronous – 32-bit address bus, 32-bit data bus – Supports single-cycle data transfers between master and slaves – Supports multiple masters, determined by arbitration implementation – Bridge function can be master on PLB or OPB – No tri-state drivers required 15 Device Control Register (DCR) Bus 16 Device Control Register (DCR) Bus • PPC405 is the only master for this 32-bit bus • DCR address is 10-bits (1024 maximum registers) • All other attached devices are slaves • Used for on-chip device configuration purposes • Doesn’t slow down high performance PLB bus • Two instructions used to access registers – Move to DCR “mtdcr” – Move from DCR “mfdcr” – Privileged mode access only! 17 Device Control Register (DCR) Bus • Transfers data between CPU general purpose registers and DCR slave registers • 3 cycle minimum read or write transfer extendable by slave or master • DCR logic must return DCRCPUACK within 64 clock cycles or processor times out. No error! CPU executes next instruction! • Slaves may be clocked slower/faster than master • IBM DCR Register Bus Architecture Specification, Version 2.8 available on the web 18 Example DCR Implementation 19 CoreConnect™ (Features) • PLB Arbiter – Arbitration for up to 8 PLB master devices on PLB bus includes watchdog timer and separate address, read, and write data paths – Supports address pipelining • PLB to OPB Bridge – PLB slave and OPB master device – Supports dynamic bus sizing for OPB connection – Supports burst reads and writes – Compliant with various bursts sizes – Supports 4-, 8-, and 16-word line transfers – Supports DMA transfers to/from OPB master peripherals 20 CoreConnect™ (Features) • OPB to PLB Bridge – PLB master and OPB slave device – 64-bit PLB master interface supports doubleword (64-bit) reads, and doubleword, word, halfword, and byte writes – Data packing on writes, up to 4-doublewords – Fixed length burst (4 doubleword) prefetching for reads 50+ MHz OPB clock frequency – Support for PLB at 1, 2, 3, or 4 times the frequency of the OPB • OPB Arbiter – Arbitration for up to 4 OPB master peripherals on OPB bus 21 Over 40 Processor IP Modules IP Function Class IP Function Class PPC405 Boot SW Only IPIF Scatter/Gather IPIF Module (HW&SW) Memory Tests SW Only PLB BRAM Memory Controller (HW&SW) BRAM SW Only PLB SRAM Memory Controller (HW&SW) SRAM SW Only PLB DDR Memory Controller (HW&SW) ZB T SW Only PLB ZBT Memory Controller (HW&SW) DDR SW Only PLB Flash Memory Controller (HW&SW) VxWorks Support SW Only OPB BRAM Memory Controller (HW&SW) VxWorks BSP SW Only OPB SRAM Memory Controller (HW&SW) Chip Support Package SW Only OPB ZBT Memory Controller (HW&SW) PLB Arbiter Infrastructure (HW&SW) OPB Flash Memory Controller (HW&SW) PLB<>OPB Bridge Infrastructure (HW&SW) Interrupt Contro ller Pe rip he ral IP Core (HW&SW) OPB Arbiter Infrastructure (HW&SW) UART Lite Pe rip he ral IP Core (HW&SW) OPB Bus Structure Infrastructure (HW&SW) UART 16450 Pe rip he ral IP Core (HW&SW) System Reset Infrastructure (HW&SW) UART 16550 Pe rip he ral IP Core (HW&SW) IPIF Slave Attachment IPIF Module (HW&SW) IIC Master & Slave Peripheral IP Core (HW&SW) IPIF Master Attachment IPIF Module (HW&SW) SPI Maste r & Slave Pe rip he ral IP Core (HW&SW) IPIF Address Decode IPIF Module (HW&SW) E the rnet 10/100M Pe rip he ral IP Core (HW&SW) IPIF Interrupt Control IPIF Module (HW&SW) A TM Uto pia Level 2 Slave Pe rip he ral IP Core (HW&SW) IPIF Read Packet FIFO IPIF Module (HW&SW) OPB Time r/Co unter Pe rip he ral IP Core (HW&SW) IPIF Write Packet FIFO IPIF Module (HW&SW) IPB Timebase/WDT Peripheral IP Core (HW&SW) IPIF DMA IPIF Module (HW&SW) OPB GPIO Pe rip he ral IP Core (HW&SW) 22 CoreConnect PLB/OPB IP Blocks IP Module Slices (Approx.) LUTs DFFs BRAMs PLB Arbiter 735 1237 234 0 PLB Bus Logic 47 95 0 0 PLB DDR SDRAM 379 279 479 0 PLB ZBT SRAM 249 97 401 0 PLB SRAM/FLASH 298 242 354 0 PLB BRAM 266 149 183 16 PLB to OPB Bridge 686 763 609 0 OPB Arbiter