25 MOSFET Current Source Equivalent Circuit ■ Small-signal model: source resistance is ro2 by inspection + r = gm2vgs2 r gm1vgs1 o1 vgs2 0 V o2 − ■ Combine output resistance with DC output current for approximate equivalent circuit ... actual iOUT vs. vOUT characteristics are those of M2 with VGS2 = VREF iOUT iOUT + (W/L) (W/L)2 2 I r v IREF REF o2 OUT (W/L) 1/ro2 (W/L)1 1 v VDS OUT − SAT2 (a) (b) EECS 105 Fall 1998 Lecture 25 The Cascode Current Source ■ In order to boost the source resistance, we can study our single-stage building blocks and recognize that a common-gate is attractive, due to it high output resistance VDD iOUT IREF M 3 M4 M1 M2 ■ Adapting the output resistance for a common gate amplifier, the cascode current source has a source resistance of ()≈ RS = 1 + gm4ro2 ro4 gm4ro4ro2 ■ Penalty for cascode: needs larger VOUT to function EECS 105 Fall 1998 Lecture 25 MOSFET Current Sources and Sinks ■ n-channel current source sinks current to ground ... how do we source current from the positive supply? Answer: p-channel current sources...? VDD M1 M2 MR M3 iOUT1 iOUT2 iOUT3 IREF ■ By mixing n-channel and p-channel diode-connected devices, we can produce current sinks and sources from a reference current connected to VDD or ground. VDD M1 MR M2 iOUT1 iOUT2 iOUT4 IREF M3 M4 EECS 105 Fall 1998 Lecture 25 Two-Stage BiCMOS Transconductance Amplifier ■ Concept: cascade two common-emitter stages to get more transconductance -- not an ideal solution but illustrates DC biasing and interstage coupling iout RS + + + vin1 vs Rin1 Rout1 Rin2 vin2 Rout2 RL _ _ _ Gm1vin1 Gm2vin2 CE (npn) CE (pnp) ■ DC Issues: First stage: npn common-emitter amplifier (DC level shifts up) Second stage: pnp common-emitter amplifier (DC level shifts down) EECS 105 Fall 1998 Lecture 25 Amplifier Topology ■ Basic structure -- connect output of CE (npn) to input of CE (pnp), attach small-signal voltage input (with RS) and load (RL) V+ = + 2.5 V iSUP1 Q2 iout RS + Q1 v s_ RL + iSUP2 _VBIAS V - = - 2.5 V ■ Current source design: assume that the reference current is generated by a resistor (to ground) EECS 105 Fall 1998 Lecture 25 DC Currents from Reference ■ p-channel diode-connected M3 is used to generate source-gate voltages for M4 (which generates iSUP1) and for M5. The second current supply is generated by first using -ID5 to generate a DC gate-source voltage via diode-connected M7. V+ = + 2.5 V M4 M3 M5 iSUP1 - ID5 IREF RREF iSUP2 ID7 M6 M7 V - = - 2.5 V EECS 105 Fall 1998 Lecture 25 Two-Stage BiCMOS Transconductance Amplifier ■ Combine current source circuit with basic amplifier topology V+ = + 2.5 V M4 M3 M5 Q2 RREF iout RS + Q1 vs _ R + L _VBIAS M6 M7 V -= - 2.5 V EECS 105 Fall 1998 Lecture 25 DC Bias of Transconductance Amplifier ■ + - Ω Given: VOUT = 0 V (DC); V = 2.5 V, V = -2.5 V; RS = RL = 50 k ■ Standard simplifications: assume IB = 0 for bipolar transistors, neglect Early effect (BJT) and channel-length modulation (MOSFETs) for hand calculations V+ = + 2.5 V M4 M3 M5 Q2 RREF iout RS + Q1 vs _ R + L _VBIAS M6 M7 V -= - 2.5 V ■ Device Properties: (for simplicity, make all n-channel and all p-channel MOSFETs the same dimensions) µ µ -2 λ -1 MOSFETs: n Cox = 50 AV , (W/L)n = (50/2), VTn = 1 V, n = 0.05 V µ µ -2 λ -1 p Cox = 25 AV , (W/L)p = (80/2), VTp = - 1 V, p = 0.05 V β β BJTs: on = 100, VAn = 50 V, op = 50, VAp = 25 V EECS 105 Fall 1998 Lecture 25 Reference Resistor ■ µ Find RREF such that IREF = 50 A and then find all node voltages and DC bias currents ... +2.5 V V + _SG3 M 3 VSG3 = VDD – IREFRREF – VSS - ID3 –ID3 0 V = – V + -------------------------------------------- SG3 Tp ()W ⁄ ()2L µ C IREF p p ox RREF - 2.5 V ■ µ Substituting IREF = - ID3 = 50 A, the source-gate voltage drop is 50 µA V ==– ()–1 V +---------------------------------------------------- 1.22 V SG3 80 2 ---------------- ()50 µA/V ()22() ■ Solve for the reference resistor: ()V – V – V () DD SS SG3 2.5 V––5 2. V– 1.22 V Ω RREF ==--------------------------------------------------- ----------------------------------------------------------------µ - =75.6 k IREF 50 A EECS 105 Fall 1998 Lecture 25 DC Operating Point ■ Since width-to-length ratios are identical for n-channel and p-channel devices (separately), the DC supply currents are equal to the reference current V+ = + 2.5 V ISUP1 = 50 µA Q2 iout RS + Q1 v s_ RL + ISUP2 = µ _VBIAS 50 A V - = - 2.5 V ■ µΑ µΑ Neglecting base currents, IC1 = 50 and IC2 = 50 Ω, ΜΩ Q1: gm1 = 2 mS, rπ1 = 50 k ro1 = 1 Ω, Ω Q2: gm2 = 2 mS, rπ2 = 25 k ro2 = 500 k Source resistances of the current supplies for first and second stages: λ -1 -1 Ω roc1 = ro4 = ( 4(-ID4)) = (0.05(0.05)) = 400 k λ -1 -1 Ω roc2 = ro6 = ( 6(ID6)) = (0.05(0.05)) = 400 k EECS 105 Fall 1998 Lecture 25 Overall Two-Port Model ■ Ω Ω Ω Ω Rin = Rin1 = 50 k and Rout = Rout2 = ro2 || roc2 = 500 k || 400 k = 220 k ■ Overall short-circuit transconductance Gm -- must apply procedure iout + + + vin1 vin Rin1 Rout1 Rin2 vin2 Rout2 _ _ _ Gm1vin1 Gm2vin2 CE (npn) CE (pnp) Find input voltage to the second stage: vin2 = - Gm1( Rout1 || Rin2 ) vin = - gm1 ( ro1 || roc1 || rπ 2 ) vin Output current iout = Gm2 vin2 = gm2 [- gm1 (ro1 || roc1 || rπ2)] vin ■ Overall transconductance: Gm = iout / vin = - gm2 gm1 (ro1 || roc1 || rπ2) Ω Ω Ω Ω Gm = - (2 mS)(2 mS)(1 M || 400 k || 25 k ) = - (2 mS)(2 mS)(23 k ) Gm = - 92 mS EECS 105 Fall 1998 Lecture 25 Output Voltage Swing ■ Find the maximum and minimum values of vOUT V+= 2.5 V M4 M3 M5 Q2 RREF vOUT Q1 + V _ BIAS M6 M7 V -= - 2.5 V ■ Determine how high the output node can rise before a device leaves its constant- current region Q2 saturates when vOUT = VOUT(max) = 2.4 V ... VEC(sat) = 0.1 V Note that M4 is still saturated since VSD4 = VEB4 = 0.7 V > vSG4 + VTp = 0.22 V ■ Determine how low the output node can drop ... M6 goes triode when vOUT = VDS7(sat) = VGS7 - VTn = 1.22 V - 1 V = 0.22 V VOUT(min) = - 2.5 V + 0.22 V = 2.23 V EECS 105 Fall 1998 Lecture 25.