October 1982 Report CSG-10 COORDINATED SCIENCE LABORATORY College of Engineering A STRUCTURED MEMORY ACCESS ARCHITECTURE Andrew Richard Pleszkim UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN Approved for Public Release. Distribution Unlimited. UNCLASSIFIED SECURITY CLASSIFICATION OF T his PAGE (When Data Entered) READ INSTRUCTIONS j REPORT DOCUMENTATION PAGE BEFORE COMPLETING FORM I. REPORT NUMBER 2. GOVT ACCESSION NO. 3. RECIPIENT’S CATALOG NUMBER 4. TITLE (and Subtitle) 5. TYPE OF REPORT & PERIOD COVERED A STRUCTURED MEMORY ACCESS ARCHITECTURE Technical Report 5. PERFORMING ORG, REPORT NUMBER CSG-10 7. AUTHORS 3. CONTRACT OR g r a n t NUMSERfs; Andrew Richard Pleszkun N00039-80-C-0556 9. PERFORMING ORGANIZATION NAME AND AOORESS 10. PROGRAM ELEMENT. PROJECT, TASK AREA 4 WORK UNIT NUMBERS Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana, Illinois 61801 11 1. CONTROLLING OFFICE NAME AND ADDRESS 12. REPORT DATS 1Q82 J Naval Electronics Systems Command YHSIC Program j 13. NUMBER OF =AG£S | 116 IS. DISTRIBUTION STATEMENT (of thia Report) Approved for public release; distribution unlimited 17. DISTRIBUTION STATEMENT (of abstract entered in 3!ock 20, ii different ‘.rom Report) 18. SUPPLEMENTARY NOTES 19. KEY WORDS ('Canfinu* on reverse side it necessary and identify by block number) Computation process Address trace analvsi: Access process Structured memory access Degree of overlap 20. ABSTRACT (C ontinue on ravers® ansa If necessary and identify by block number) When conventional von Neumann architectures reference the memory, addressing information must first be obtained, usually by transfer from tr.e memory to the CPU. TVihe work performed by the CPU can be part it toned into a computation process and an access process. Outside or adding addressing modes to instructions, little has been done to reduce the work performed by the access process or to reduce the demands placed on the memory tor access —re rated activities. This work investigates one method of reducing the von Neumann F CRM DD I J AN 733 1473 SECURITY CLASSIFICATION Or THIS 3 AG E ’Wren Data Entered; SECURITY CLASSIFICATION OF THIS PAGEfWxwi Date Entered) bottleneck and improving the degree of overlap between the computation and access processes. Program referencing behavior is first studied by analyzing program address traces. With the information gained from the address trace analysis, a Structured Memory Access (SMA) architecture is developed which makes fewer references to memory and permits the access process to be, by and large, decoupled from the computation process, thus providing a maximum degree of overlapped execution and access prediction. To evaluate the effectiveness of the SMA architecture in reducing addressing overhead, a comparison is made between a hypothetical SMA machine and a VAX-like machine with respect to the number of memory references generated by a set of programs. Depending on the program, the SMA machine reduced the number of memory references to between 1/5 and 2/5 of those required by a conventional VAX. An estimate is also made of an SMA machines performance relative to that of a VAX. A machine's performance is parameterized by the memory bandwidth and the computational overhead. It was found that performance is very sensitive to these parameters; however, an SMA machine performs significantly better than a conventional machine with the same parameters. The SMA architecture reduces addressing overhead and provides improved system performance by (1) efficiently generating operand requests, (2) making fewer memory references, and (3; maximizing computation and address generation overlap. I A STRUCTURED MEMORY ACCESS ARCHITECTURE BY ANDREW RICHARD PLSSZKUN B.S., Illinois Institute of Technology, 1977 M.S., University of Illinois, 1979 THESIS Submitted in partial fulfillment of the requirements the degree of Doctor of Philosophy in Electrical Engineering in the Graduate College of the University of Illinois at Urbana-Champaign, 1982 Urbana, Illinois A Structured Memory Access Architecture Andrew Bichard Pleszkun, Ph.D, Department ox" Electrical Engineering University of Illinois at Urhana-Champaign, 1982 When conventional von Neumann architectures reference the memory, addressing information must first be obtained, usually by transfer from the memory to the CPU. The work performed by the CPU can be partitioned into a computation process and an access process. Outside of adding addressing modes to instructions, little has been done to reduce the work performed by the access process or to reduce the demands placed on the memory for access-related activities. This work investigates one method of reducing the von Neumann bottleneck and improving the degree of overlap between the computation and access processes. Program referencing behavior is first studied by analysing program address traces. With the information gained from the address trace analysis, a Structured Memory Access (SMA) architecture is developed which makes fewer references to memory and permits the access process to be, by and large, decoupled from the computation process, thus providing a maximum degree of overlapped execution and access prediction. To evaluate the effectiveness of the SMA architecture in reducing addressing overhead, a comparison i3 made between a hypothetical SMA machine and a YAX-like machine with respect to the number of memory references generated by a set of programs. Depending on the program, the SMA machine reduced the number of memory references to between 1/5 and 2/5 of those required by a conventional YAX. An estimate is also made of an SMA machines performance relative to that of a VAX, A machine’s performance is parameterized by the memory bandwidth and the computational overhead. It was found that performance is very sensitive to these parameters; however, an SMA machine performs significantly better than a conventional machine with the same parameters. The SMA architecture reduces addressing overhead and provides improved system performance by (1) efficiently generating operand requests, (2) making fewer memory references, and (3) maximising computation and address generation overlap. i i i ACKNOWLEDGMENT The author wishes to express his gratitude and appreciation to his thesis advisor Professor Edward S. Davidson. Professor DavidsonTs patient guidance and helpful suggestions were invaluable contributions to this work. His insight, encouragement, and concern were indispensable sources of support throughout the author's period of study. The author would also like to thank his colleagues in the Computer Systems Group at the Coordinated Science Laboratory and Professors B. H. Rau, J. A. Abraham, J. H. Patel, and M. S. Schlansker for their friendship and the stimulating intellectual atmosphere which they provided. Finally, the author wishes to thank his parents and family for their continual support and encouragement. iv TABLE OF CONTENTS Page 1. INTRODUCTION 1 1.1 The von Neumann Bottleneck ........ ........... ............ 1 1.2 Conventional Answers to the von Neumann Bottleneck ....... 5 1.3 Background for the Structured Memory Access (SMA) Approach. ................... ......................... •..... 7 2. PROGRAM TRACE ANALYSIS ............... ........................ 15 2.1 Instruction Analysis ............................ ........ 17 2.2 Data Analysis .... ......................................... 22 STRUCTURED MEMORY ACCESS MACHINE (SMA) a r c h : 4. AN SMA IMPLEMENTATION *17; 4.1 Data Referencing .................... 48 4.1.1 Data Types .......................................... 43 4.1.2 Immediate and Scalar Operands ....................... 49 4.1.31Data Structure and Index Operands .................. 51 4.2 Control Issues ............................................ 53 4.2.1 Instruction Fetching and Operand Request Servicing .. 60 4.2.2 Branching ............. 63 4.2.3 The Computation Processor ........... ............... 7^ 4.2.4 Subroutine Call3 .................................... 76 4.3 A Sample SMA Program ................. 78 5. SMA EVALUATION ................................................ 39 5.1 Number of Memory References Generated ...................... 93 5.2 An Estimate of Relative Performance ........................ 101 6. CONCLUSIONS 110 5.1 Summary of Results ............ ........................... 110 6.2 Suggestions for Future Research ........................... 112 REFERENCES ........................................................ 114 V LIST CF FIGURES 1 -1. CPU-Memory Model ................... .................... 2 1-2. Segmented RAM ............................. .............. 10 1- 3* Successor Accessed Memory ................... .......... 12 2- 1. The number of blocks with a particular length ......... 19 2-2. The total number of times a blocks of a particular length is executed .................. .................. ........ 20 2-3. Sample data address list ................................ 26 2- 4. Data address list analysis .............. .............. 30 3- 1 . SMA organization ........................ .............. 41 4- 1. MAP internal organization .............................. 59 4-2. The operand and instruction buffer ...................... 62 4-3. The read and write queues .............. ................. 66 4-4. The access pattern and access information tables ....... 80 4- 5. Sample SMA program listing ....... ..................... 33 5- 1. Instruction blocks for Gaussian elimination .............. 91 5-2. Instruction blocks for quicksort ...... ................