no LSI. :,.....- The_S_par_KIT__C_hiP_5et \ ; \ ; The SparKIT Chipset LSI: The Complete SPARC Solution Page 1 ｔｨ｣｟ｓｾｰ｡ｲＭｋｉｔＭ LSI. ...-Chi-·psc_t • Background • SBus and Mbus • The SparKIT Chipset • System Integration 4.8 LSI. The_s_par_KIT_N_Chi_·JlSC_l SPARCstation Architecture ZS530 sec . serial port A serial port B ZS530 sec keyboard mouse 8-bit 79C30 ISDN audio input bus audio output 48T02RTC .Ｎｳｈｵｳｾ｢ｩｴ ｴｾ［ｴｙｬ｡･ｯ｣｡ｲ､ ... ＺＺｩ［Ｚ［ＡﾷｪｾＲＤﾷＺｳＺ［Ａ Boot PROM 82072 FDC floppy disk LSI: The Camplcte SPARe Solution msw 7/15/91 Page 3 LSI. The_s_par_KIT_NCbi_·_psel SBus Features • Synchronous I/O Bus • Up to 25 MHz bus clock frequency • 32-bit Data bus • 32-bit Virtual Address for SBus masters • Geographical device selection • Supports Burst transfers up to 64 bytes • Error and Rerun protocols • Supports up to 8 masters 4.9 LSI: 11ae CGmpIcc SPARe SaIaIiaa ""11St191 ftI LSI. Tbe_spar_KIT__Chi_opset The SparKIT' Architecture Memory CPU Array Module ZSSC30SCC serial port A serial port B ZSSC30SCC keyboard mouse Boot PROM 82077AFDC floppy disk drive 48T02RTC SparKIT-40 Family I,<q 79C30AISDN LSI: The Complete SPARe Solution msw7/1S/91 PlgeS ｔ｢･｟ｓｾ LSI. __Cb_Iipse_1 The SparKIt Advantage • Modularity: Plug different CPU Modules with different speeds and Implementations • Standards: 3rd party SBus Cards and Mbus Modules • Simplicity of Interface: Mhus and SBus synchronous interfaces provide a simple high speed interface to other busses (i.e. Futurebus+, VME) • HighIntegration:Reduction in overall system cost 4.10 ---------------------------- h LSI. The_SJl8f_KlT_Chipscl_"_ Mbus Features • Synchronous Multiprocessor/Memory Bus • High speed, up to 40 MHz bus clock frequency • 64-bit data bus • Multiplexed Address & control/Data bus • 36-bit Physical Address (up to 64 Gigabytes) • Supports Burst transfers up to 128 bytes • Supports Multiple Masters • Error and Rerun protocols LSI: The Complele SPARe Solution msw711S191 Pqe7 LSI. 1'bc_SJl8f_ICIT_-_OIi_"pset Mbos Transactions: Read eLK 1'----.....-----.J1 ｭｩｇ｟ｾＭＭＭＭｾＭＭＭＢＢＡＢＢＭＢＧＭＭＭ｟Ｋ｟ＭＭＭ｟Ｋ｟｟ Word Read (Mhus Request and Grant, not shown) 4.11 ....7/15191 LSI. -------------------The-S-PII'-Krr-"'-Chi-opsc-t \ ' Mbus Transactions: Write \ 2 3 4 5 6 7 9 10 ClK iL-J gAt) ｾｾ d_1 ｾ d2 _ \ : \\....--------- Word Write (Mbus Request and Grant, not shown) LSI: The Compler.c SPARC Solution msw7ns191 Pqe9 ftl o LSI. The_SPII'...K1T__Chi_pIC_t Mbus Transactions: Burst Read i 1 2 ! 3 5 6 1 7 8 9 10 11 CLK MAS' L-JJ MAD •••ｉＺＡｐＬｾｾＱＺｊ ｾ､ｾＱＮｾ､ＲｴｸＺｾｾｾｾｾ､ＷｾＮｾ､ＸｾＮｉｩｉ •• MmWI ＧＭＭｾＭＭＭＭＢＢＧＭＭＭＭＭＧＨ tOri I MRT'YI 1 DB ｵＭｬｩＭＭｾ ｾ __--";' ｾ｟Ｍｊ ｾＭＭＭｾＭＭＭｾＭＭＭｾＭＭＭ｟｟ＴＭＭＭＭＭＭＭＭ imG &...1 MB'AI Burst Read (Mbus Request and Grant, not shown) 4.12 LSI: neCaDpIeIe SPARe SoIuIiaD "'.0 LSI. The_s_par_KIT_"'_Chi_o_psct Mbus Transactions: Bus Arbitration 2 i 3 4 i 5 6 i 7 8 9 10 i 11 12 i 13 14 15 16 17 18 elK u U1 . : : ; Dev 0 has the bus, it assens Dev 1requestS the bus, when Dev 0 de- /MBB. The Mbuscontroller assens /MBB, the Mbus controller grants has assened /MBGO the bus to Dev 1 by asserting /MBG1 and de-assening /MBGO LSI: The Complele SPARC Solution msw7/1S191 Page 11 LSI. The_S_pIJ'_KIT_"'_Cbi_"psc_t SparKIT • CPU core chips L64811 Integer Unit (lU) L64814 Floating Point Unit (FPU) L64815 MMU, Cache Control, Cache Tags (MCT) • Peripheral chips L64850 DRAM Memory Controller (DMC) L64851 Peripheral Controller (STDIO) L64852 Mbus to SBus Controller and 10 MMU (M2S) L64853ASBus DMA Controller 4.13 LSI: 'DIe QIIIIpIllIe SPARe SoIuaion PlF12 LSI. The_S_pal_KIT_N_Chi_opsct L64811 Integer Unit • 136 general purpose registers • 8 overlapping register windows • 2 coprocessor interfaces Floating point unit User definable coprocessor • Operating frequency: 25, 33, 40 MHz • Performance: 18-29 MIPS LSI: The Complet.e SPARC Solution msw7nS191 Page 13 ftl o LSI. 1'be_s_pm'_KIT__Cbi_JllCl_ L64814 Floating Point Unit • Single chip floating point coprocessor • Interfaces directly to L64811 Integer Unit • 64-bit internal data path for all operations • IEEE exception handling directly in hardware • Operating frequency: 25, 33,40 MHz • Performance up to 6.0 MFlops @ 40 Mhz 4.14 LSI: DeCompIeIe SPARe SoIuIiaD PIp 14 LSI. The_spar_KIT_no_Chi_"pset L64815 MMU, Cache Controller, Tags (MeT) • SPARC reference MMU compatible • Address Translation performed by Hardware (tablewalk) • 64 entry TLB utilizing LRU replacement Algorithm • Write through Cache Controller • 64K and 128K Cache size support • 2048 On-Chip Cache Tags • Support for Cypress, Motorola and 386 type S.RAMs • High performance 64-bit Mbus • Support of Block Copy and Block Zero functions • Operating frequency 25,33,40 MHz LSI: The Complete SPARe Solution msw7/1S191 Page 15 no LSI. The_SPBI'_KIT__Chi_·p5Ct MeT Block Diagram Data Ｎ｡Ｍ｟ｾ __(31:0) ｾｾ ---. Cache RAM Translation Lookaside Buffer (TLB) Address Bus IIEXOt-+-__ｾ ItIT'......- __ｾ Mbus FPU MAD(63:0) Main Memory IU Ul:neCOmpIae SPARe 5oIuIion PIle 16 4.15 LSI. The_S_JIII'_KJT_""_Chi_opsel L64852 Mbus to SBus Controller (M2S) • Provides Mbus Arbitration • Provides SBus Arbitration • On-board I/O MMU for SBus DVMA masters • Mbus to SBus protocol conversion • 32 Mbytes I/O space • PerfoIm Split-Read, Buffered Writes to optimize bus B/W • Contains Watchdog timer LSI: The Complete SPARe Solution msw7nS191 Page 17 LSIIItII 1be_S_JIII'_KJT_ftl_Cbi_OI*l_ ... M2S Block Diagram Mbus . -- T t - 1 IMbus Arbiter __ IMbus Interface I--- Control va Data Buffer Protocol Logic MMU 2x32 bytes Conversion I SBus Arbiter I --I SBus Interface I--- 4 SBus • 4.18 LSI: 'heCcIaIpIeIie SPARe SoIuIaa PIp IS LSI. The_SF_KIT_NChi_"_psct MBus Support MBus Arbiter • Supports Up to Four MBus Masters (i.e. M2S and three CPUs) • Linear and Round Robin Prioritization Scheme • MBus Master in M2S Receives Highest Priority (Ethernet Latency) • Round Robin Arbitration Used for All Other MBus Masters • Provides MBus Request and Grant Lines for Each Master • Observes Bus Parking Feature Used by MBus Protocol LSI: The Comp1ele SPARC Solution msw 7/15/91 Page 19 LSI. The_SF_KIT_'"'_Chi_"psct SBus Support SBus Arbiter • Supports Up to Six SBus Masters (Le. M2S, DVMA, and four Slots) • Linear and Round Robin Prioritization Scheme • DVMA Receives Highest Priority (Ethernet Latency Requirements) • Round Robin Arbitration Used for All Other SBus Masters • Provides SBus Request and Grant Lines for Each Master 4.17 LSI: 'I1IIc CCImpIeIe SPARe SoIuIion IIISW 7/lSt'91 Pqe20 N LSI. The_SJIU'_KIT__C_hiplet_ I/O Memory Management Unit Overview • Provides Virtual to Physical Address Translation • Allocates Upper 32-Mbytes of the 4-Gbyte Virtual Address Space for I/O Devices Residing on SBus • Allows for Single I/O Process Allocation of All 32-Mbytes • Page Size Configuration of 4-Kbytes • Single-Level Page Table Entry (PTE) • Contains a 16 entry LRU TLB for I/O MMU LSI: The Complete SPARC Solution msw 7/15191 Page 21 N LSI. The_SP'I'_KIT__Cbi_·pIet_ L648S0 DRAM Memory Controller (DMC) • Supports 1M x 9 and 4M x 9 DRAM Modules • ｓｵｰｰ｣ｾｳ up to 64 Mbytes total Memory space • ｓｕｐｐｾＢﾷＺＱｓ Up to 2 banks (8 bytes/bank) • Fast Page Mode (Mhus Burst transfers) • On-board Data buffers • Parity Error detection • Cascadable • Implements CAS before RAS Refresh scheme 4.18 --------------------------"22 LSI. l The SparKITlII_Chipset L64851 Peripheral Controller (STDIO) • Supports up to eight 8-bit Slave-type peripherals (I/O) • Provides 64-bit Mbus interface to I/O devices • 8-byte packing/unpacking • Provides Interrupt Level encoding for up to 13 devices • Provides 1 Megabyte address space per I/O device (8 Mbytes total) • Contains Mbus Arbiter and Time-out Functions • Up to 40 MHz maximum clock frequency LSI: The Camplele SPARC Solution msw 7/15/91 Page 23 LSI. The_SJlIIII'_KIT_no_Chi_opsct L64853/A SBus DMA Controller • Single chip SBus Interface • Supports 8/16-bit peripherals • Handles 32-bit packing and unpacking • Support for 16byte SBus Burst transfers • Support for DMA chaining • Supports byte, half word, or word transfers on SBus • Supports SBus Rerun Acknowledgments • 25 MHz clock frequency • Low cost 120-pin Plastic Flat Pack (PQFP) package 4.19 LSI: 11Ie CaaIpIec SPARC SoIuIion .-w7115J91 LSI. The_spar_KIT_'"'_Chi_opscl_ The Rest of the Complete Solution • Schematics (Manufacturing Kit) • SunOS Port ··1: The ComplelC SPARe Solution msw711S191 Pagc2S 4.20.