TMS320DM35x Digital Media System-on-Chip (DMSoC) Video Processing Back End Reference Guide Literature Number: SPRUF72C October 2008 2 SPRUF72C–October 2008 Submit Documentation Feedback Contents Preface....................................................................................................................................... 14 1 Purpose of the Video Processing Back End........................................................................... 18 1.1 Features .................................................................................................................. 18 1.2 Functional Block Diagram .............................................................................................. 21 1.3 Supported Use Case Statement....................................................................................... 21 1.4 Industry Standard(s) Compliance Statement ........................................................................ 21 2 Display Subsystem Environment.......................................................................................... 21 2.1 Analog Display Interface................................................................................................ 23 2.2 Digital Display Interface................................................................................................. 32 2.3 VPBE Display Subsystem I/O Multiplexing........................................................................... 44 3 VPBE Integration................................................................................................................ 47 3.1 Clocking, Reset, and Power Management Scheme ................................................................ 47 3.2 Hardware Requests ..................................................................................................... 53 3.3 Video DAC Configuration............................................................................................... 53 3.4 VPBE Top-Level Register Mapping Summary....................................................................... 56 4 VPBE Functional Description............................................................................................... 56 4.1 Block Diagram ........................................................................................................... 56 4.2 Interfacing with Displays ................................................................................................ 57 4.3 Master/Slave Mode Interface .......................................................................................... 61 4.4 On-Screen Display (OSD) Module .................................................................................... 62 4.5 Video Encoder Module ................................................................................................ 102 5 Programming Model.......................................................................................................... 138 5.1 Setup for Typical Configuration ...................................................................................... 138 5.2 Resetting the VPBE Subsystem ..................................................................................... 138 5.3 Configuring the Clocks and Control Signals........................................................................ 138 5.4 Programming the On-Screen Display (OSD)....................................................................... 139 5.5 Programming the VENC............................................................................................... 146 6 VPBE Registers ................................................................................................................ 152 6.1 VPSSCLK - VPSS Clock Controller ................................................................................. 152 6.2 VPSSBL - VPSS Buffer Logic ........................................................................................ 155 6.3 On-Screen Display (OSD) Registers ................................................................................ 162 6.4 Video Encoder/Digital LCD Subsystem (VENC) Registers ....................................................... 206 Appendix A Revision History ..................................................................................................... 249 SPRUF72C–October 2008 Table of Contents 3 Submit Documentation Feedback www.ti.com List of Figures 1 Functional Block Diagram ................................................................................................. 17 2 Video Processing Subsystem Block Diagram .......................................................................... 18 3 Video Processing Back End Block Diagram ............................................................................ 21 4 Horizontal Timing........................................................................................................... 24 5 NTSC Vertical Timing...................................................................................................... 27 6 PAL Vertical Timing ........................................................................................................ 28 7 100% Color Bar Output Level ............................................................................................ 30 8 75% Color Bar Output Level .............................................................................................. 31 9 YCC16 Output for Normal OSD Operation ............................................................................. 35 10 YCC16 Output When OSD Window in RGB565 ....................................................................... 35 11 YCC8 Output for Normal OSD Operation ............................................................................... 38 12 YCC8 Output When OSD Window in RGB565......................................................................... 38 13 RGB Output in Parallel RGB Mode ...................................................................................... 40 14 PINMUX1 Register ......................................................................................................... 45 15 VPBE/DAC Clocking Options ............................................................................................. 48 16 VPSS Clock Mux Control Register (VPSS_CLK_CTRL).............................................................. 49 17 USB Physical Control Register (USB_PHY_CTRL) ................................................................... 50 18 Video DAC Configuration Register (VDAC CONFIG) ................................................................. 54 19 Video Processing Subsystem Block Diagram .......................................................................... 56 20 Video Processing Back End Block Diagram ............................................................................ 57 21 Video Encoder Display Frame and Control Signal Definitions ....................................................... 61 22 OSD Window Display Priorities........................................................................................... 62 23 OSD Window Positioning.................................................................................................. 65 24 OSD Window Frame Mode ............................................................................................... 67 25 OSD Window Field Mode ................................................................................................. 68 26 OSD Window Zoom Process ............................................................................................. 70 27 Video Window Display Options........................................................................................... 74 28 Pixel Arrangement in the Display ........................................................................................ 74 29 Video Data Format – YUV422............................................................................................ 74 30 Filtering Method for Horizontal x2/x4 Zoom ............................................................................ 76 31 Filtering Method for Horizontal x1.5/x1.125 Zoom ..................................................................... 77 32 Filtering Method for Vertical x1 Expansion (Same Data Each Field)................................................ 78 33 Filtering Method for Vertical x1 Expansion (Frame Data)............................................................. 79 34 Filtering Method for Vertical x2 Expansion (Same Data Each Field)................................................ 80 35 Filtering Method for Vertical x2 Expansion (No Field Rate Conversion) ............................................ 81 36 Filtering Method for Vertical x2 Expansion (Frame Data)............................................................. 82 37 Filtering Method for Vertical x4 Expansion (Same Data Each Field)................................................ 83 38 Filtering Method for Vertical x4 Expansion (No Field Rate Conversion) ............................................ 84 39 Filtering Method for Vertical x4 Expansion (Frame Data)............................................................. 85 40 Filtering Method for Vertical x1.2 Expansion with No Zoom.......................................................... 86 41 Filtering Method for Vertical x1.2 Expansion with 2x Zoom .......................................................... 87 42 Filtering Method for Vertical x1.2 Expansion with 4x Zoom .........................................................