IT 16046 Examensarbete 30 hp Juni 2016 The Timing and Fast Control Demonstrator Jiheng Chen Vasileios Filos Institutionen för informationsteknologi Department of Information Technology Abstract The Timing and Fast Control Demonstrator Jiheng Chen and Vasileios Filos Teknisk- naturvetenskaplig fakultet UTH-enheten In this thesis, the feasibility of an FPGA to host a system for generating and distributing clocks as well as distributing synchronous and Besöksadress: asynchronous commands is tested. This system will be an imitation of the Ångströmlaboratoriet Lägerhyddsvägen 1 SHiP (Search for Hidden Particle) DAQ (Data Acquisition) system led by CERN. Hus 4, Plan 0 The practical implementation is to mainly apply Altera Cyclone V GT development board attached with SFP+ daughter card to achieve accurate Postadress: timing and high speed performance. Box 536 751 21 Uppsala Experiments include three loopback test implementations. Loopback test is the simplest technique to assess a channel’s integration. The first one is Telefon: the Ethernet loopback test. An Ethernet card daughter board is inserted to 018 – 471 30 03 the HSMC port of the Cyclone V GT development board. After that, a SFP card Telefax: is applied alternatively on the same port to do the similar loopback test 018 – 471 30 00 but at a much higher speed via optical fibers. And finally, a more advanced XAUI to SFP+ card daughter board will be used to replace the previous SFP Hemsida: card in order to get a further speed improvement at around 10Gbps. The last http://www.teknat.uu.se/student part is being implemented to check whether the system can distribute clock and data even on higher transfer rates. An alternative, more appropriate, DE4 FPGA development board is also used for the last experiment part apart from Cyclone V. The system is implemented by Altera Cyclone V GT board, Altera DE4 board, Terasic Ethernet-HSMC board, Terasic SFP-HSMC card and Dual XAUI to SFP+ HSMC card. The design is built and programmed by the Quartus II 13.1 and Nios II Software Build Tool. Some embedded tools of Quartus for test and verification are used including Transceiver Toolkit and SignalTap II Logic Analyzer. Handledare: Leif Gustafsson Ämnesgranskare: Pawel Marciniewski Examinator: Arnold Neville Pears IT 16046 Tryckt av: Reprocentralen ITC Acknowledgments We would like to express our deepest appreciation to our supervisor Leif Gustafsson and our reviewer Pawel Marciniewski for their continuous guidance and persistent help during this thesis until the very end of it. Also, many thanks go to our friends and colleagues for their useful feedback and help, during our thesis. Last but not least, we would like to thank our families for their support and trust during our whole studying career. Without them, we would not have reached this point. Contents Chapter 1 .............................................................................................................................. 1 1.1 Introduction .......................................................................................................................... 1 1.2 Motivation ............................................................................................................................. 1 1.3 Objectives ............................................................................................................................. 2 Chapter 2 Background .................................................................................................... 3 2.1 OSI model ............................................................................................................................. 4 2.1.1 Physical Layer ............................................................................................................. 4 2.1.2 Data Link Layer ........................................................................................................... 5 2.1.3 Network Layer ............................................................................................................. 5 2.2 Ethernet Protocol ............................................................................................................... 5 2.3 Optical Fibers ...................................................................................................................... 7 2.4 GBT ........................................................................................................................................ 9 2.4.1 GBT-FPGA Core ........................................................................................................ 10 2.4.2 GBT-FPGA Block Diagram ..................................................................................... 11 2.5 MicroPOD ............................................................................................................................ 13 2.6 Quantum Dots ................................................................................................................... 13 Chapter 3 Hardware and Software ................................................................................. 9 3.1 Hardware ............................................................................................................................... 9 3.1.1 Cyclone V GT ............................................................................................................... 9 3.1.1.1 Overview ............................................................................................................... 9 3.1.1.2 FPGA .................................................................................................................... 10 3.1.1.3 Clocking .............................................................................................................. 10 3.1.1.4 Gigabit Ethernet PHY ....................................................................................... 11 3.1.1.5 HSMC ................................................................................................................... 11 3.1.1.6 Transceivers PLLs ............................................................................................ 12 3.1.2 DE4 Development Board ........................................................................................ 13 3.1.2.1 Overview ............................................................................................................. 13 3.1.2.2 FPGA .................................................................................................................... 14 3.1.2.3 Clocking .............................................................................................................. 14 3.1.2.4 Gigabit Ethernet PHY ....................................................................................... 14 3.1.2.5 HSMC ................................................................................................................... 14 3.1.2.6 Transceiver PLLs .............................................................................................. 15 3.1.3 Device Comparison .................................................................................................. 16 3.1.4 Ethernet HSMC Card and Marvel 88E1111 Controller ..................................... 17 i 3.1.5 SFP-HSMC Card ........................................................................................................ 18 3.1.6 DUAL XAUI to SFP+ HSMC Board ........................................................................ 20 3.2 Software .............................................................................................................................. 22 Chapter 4 Transceivers Datapath ..................................................................................23 4.1 Standard Transceiver Datapath .................................................................................... 23 4.1.1 Transmitter (TX) ........................................................................................................ 23 4.1.1.1 Phase Compensation FIFO ............................................................................ 23 4.1.1.2 Byte Serializer.................................................................................................... 24 4.1.1.3 8b/10b Encoder ................................................................................................. 24 4.1.1.4 Bit Serializer (SerDes) ..................................................................................... 28 4.1.2 Receiver (RX) ............................................................................................................. 28 4.1.2.1 Receiver CDR ..................................................................................................... 28 4.1.2.2 Bit Deserializer (SerDes) ................................................................................. 28 4.1.2.3 Word Aligner ...................................................................................................... 29 4.1.2.4 Deskew FIFO ...................................................................................................... 29 4.1.2.5 Rate Matcher ...................................................................................................... 30 4.1.2.6 8b/10b Decoder ................................................................................................. 30 4.1.2.7 Byte Deserializer ............................................................................................... 30 4.1.2.8 Byte Ordering ...................................................................................................