Lining Zhang · Mansun Chan Editors Tunneling Field Effect Transistor Technology Tunneling Field Effect Transistor Technology Lining Zhang • Mansun Chan Editors Tunneling Field Effect Transistor Technology 123 Editors Lining Zhang Mansun Chan Hong Kong University of Science and Hong Kong University of Science and Technology Technology Hong Kong Hong Kong China China ISBN 978-3-319-31651-2 ISBN 978-3-319-31653-6 (eBook) DOI 10.1007/978-3-319-31653-6 Library of Congress Control Number: 2016935208 © Springer International Publishing Switzerland 2016 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG Switzerland Preface Power consumptions have been a dominant constraint in nanoscale CMOS tech- nologies. Different techniques to reduce computational power spanning from the architecture level to the fundamental semiconductor devices level are actively explored. One possible solution from the device perspective is to decrease the operation voltage without sacrifice of the switching properties. While its applica- bility was proved from the circuit theory, a lot of efforts in the electron device society have been gathered on devices with possible steep slopes that go beyond the traditional MOSFETs. Tunnel field-effect transistors are one representative of the steep slope devices. Their operations are based on the controlled switching of quantum tunneling, instead of the thermionic emissions. Historically, the study of similar concept may date back to the 1970s when the physicist used the gated tunnel junction to study the two-dimensional electron gas. Later, in the 1980s the interband quantum tunneling was observed in a DRAM trench transistor and people started to think about a device concept based on controlled interband tunneling. More device proposals followed in the 1990s. In 2004, a steep slope of 40 mV/dec was observed in carbon nanotube transistors and was attributed to the band-to-band quantum tunneling. At almost the same time people were intensively looking for solutions of the ever-increasing CMOS power problem. Since then the tunneling field-effect transistor (TFET) or devices with equivalent mechanisms but different names bloomed and attracted wide attention from the electronic device community as a promising low power device. Till date, TFET is an active research topic and is attracting attention from the industry for further development. Knowledge sharing among different researchers, including people working on the device process, people working on device physics and modeling, people working on circuit designs, and people working on new materials and physics is an essential accelerator to incubate the technology and push it from research to applications. There are seven chapters in this book covering the TFET fabrications, TFET modeling, and also simulations of the TFET-based circuit design techniques. Chapter 1 covers a review of the steep slope devices including TFET. A holistic review on the research background and six kinds of steep slope devices are v vi Preface provided. After brief introductions to each device’s operations and the latest advances, a more detailed discussion of the TFET operation and several TFET performance boosters are summarized. Chapter 2 reviews the fabrication process and characterization methods of a variety of TFETs. Starting from the conventional lateral p-i-n TFET, the chapter discusses the tunnel junction formations including the doped junctions and the doping-less electron-hole bilayer. Going forward, the chapter summarizes the TFETs of homojunction and heterojunction, with material systems from Si/Ge, III–V compound semiconductors to the latest transition metal dichalcogenides. Characterization methods of the TFETs threshold voltages and subthreshold swings are provided. Chapter 3 discusses the compact models of TFETs. After providing a brief review of the TFET modeling in the literature, a complete SPICE model including the descriptions of current-voltage and charge-voltage characteristics are formulated based on detailed investigations of the TFET operations. Advanced effects in TFETs like the gate leakage and short channel effects are further discussed toward a full compact model. Challenges in the heterojunction TFET modeling are briefly discussed. Chapter 4 focuses on the challenges and designs of TFET-based digital circuits. Although promising for low voltage operations, TFETs have unique properties like unidirectional conduction, delayed saturation, enhanced Miller capacitance, imbalanced complementary logic, and larger variations. After describing these design challenges, the chapter proposes the all n-type pass-transistor logic to bypass the imbalanced complementary issue and the dual oxide device design to mitigate the issues due to enhanced Miller capacitances. Designs of the SRAM are investigated with a proposal of hybrid TFET–MOSFET cell. Chapters 5–7 cover more fundamental physics properties and the device designs of advanced TFETs. Chapter 5 reviews two atomistic simulation methodologies, namely the density functional theory (DFT) and tight binding (TB) within the Keldysh nonequilibrium Green’s function (NEGF) framework. A new nonequilibrium vertex correction method is integrated with the NEGF-DFT to study disorder scattering in graphene TFETs. The NEGF-TB method is demonstrated by simulating the electric characteristics of a monolayer transition metal dichalcogenide TFET. Chapter 6 introduces another atomistic simulation method, the reduced-order k Á p method, to accelerate the three-dimensional quan- tum transport study of TFETs. Basic theoretical background of the eight-band k Á p Hamiltonian and the reduced-order NEGF equation, together with the spurious band elimination are described. The method is used to study the InAs-based homojunction TFET and the GaSb/InAs heterojunction TFET. Chapter 7 covers the device designs and optimizations of the carbon nanotube TFETs with the NEGF-TB method. After introducing the basic carbon nanotube properties, the chapter goes on to discuss device operation mechanisms. Doping engineering and gate dielectric engineering are developed to enhance the TFET performances. A barrier-controlled TFET is also proposed theoretically based on the atomistic simulations. We are deeply grateful to all the chapter authors for their great efforts and outstanding chapters. When initiating this book on the tunneling field-effect tran- sistor technology, all authors agreed that it was the right time to review the research Preface vii efforts on TFETs of the past decade and to gather together the latest research results. Bearing this in mind, every author spent their valuable time as a promise to make a comprehensive, authoritative, insightful, and up-to-date book for the purpose of knowledge sharing and dissemination. We sincerely hope that this edited book can serve as a platform for readers to have access to the current full frame of the tunneling field-effect transistor technology and to stimulate further interests into the next stage. Clear Water Bay, Hong Kong Lining Zhang Mansun Chan Contents 1 Steep Slope Devices and TFETs ........................... 1 Lining Zhang, Jun Huang and Mansun Chan 2 Tunneling FET Fabrication and Characterization .............. 33 Tao Yu, Judy L. Hoyt and Dimitri A. Antoniadis 3 Compact Models of TFETs............................... 61 Lining Zhang and Mansun Chan 4 Challenges and Designs of TFET for Digital Applications ........ 89 Ming-Long Fan, Yin-Nien Chen, Pin Su and Ching-Te Chuang 5 Atomistic Simulations of Tunneling FETs .................... 111 Fei Liu, Qing Shi, Jian Wang and Hong Guo 6 Quantum Transport Simulation of III-V TFETs with Reduced-Order k Á p Method .......................... 151 Jun Z. Huang, Lining Zhang, Pengyu Long, Michael Povolotskyi and Gerhard Klimeck 7 Carbon Nanotube TFETs: Structure Optimization with Numerical Simulation ............................... 181 Hao Wang Index ................................................. 211 ix Chapter 1 Steep Slope Devices and TFETs Lining Zhang, Jun Huang and Mansun Chan Abstract Reducing energy dissipations per function with the integrated circuit (IC) chips is always an appealing research topic. Techniques in the fundamental electronic device levels are being pursued besides of those in the architecture level. In this chapter, we introduce several device candidates with a