By Whitney Zack and Wade Campney Key points Problem with Memory Non‐Volatile Memory à MRAM Volatile Memory à SRAM à DRAM Hybrid/Hyper Memory Cube (HMC) à Design à Performance RAM The Problem with Memory Memory performance is not scaling to Moore’s Law (CPU performance.) This creates a bottleneck in performance. Some call this a “memory wall” Conventional memory architectures Memory I/O performance/bandwidth cannot keep up Problems with heat and power consumption when adding more memory or moving it closer to CPU Non‐Volatile Is computer memory that can retain the stored information even when not powered à MRAM à FeRAM à PRAM MRAM: “Universal Memory” Magnetoresistive Random Access Memory Magnetic cells instead of electric charge Slower than SRAM Low voltage, and low cell leakage. Similar density compared to DRAM MRAM Drawbacks Requires a lot of current to write to memory Requires big cell size to prevent the ‘half‐ select problem’ No plans for FAB quite yet due to other memory demands(Flash/DRAM) MRAM: Toggle Mode Cell is modified to contain an artificial antiferromagnet layer. Resulting layers only have two stable states, which can be toggles by skewing the write currents to “rotate” the field. This fixes the half‐select problem and allows for smaller MRAM cells. MRAM: Toggle Mode(PIC) MRAM: Spin Transfer Torque This method uses spin‐aligned electrons to directly torque the domains. Lower amount of current required to write to the cells. Allows for even smaller cell sizes(~65nm), which allows for a higher density. MRAM Spin Transfer(PIC) Volatile Memory Retaining data only as long as there is a power supply connected à SRAM à DRAM à Hybrid Memory Cube SRAM(Static RAM) drawbacks 4‐6 transistors to create a single bit of SRAM SRAM takes up much more space than DRAM SRAM is byte for byte more expensive than DRAM No leaking like in DRAM so there is no need for refresh circuit Flip Flop design allows for instantaneous written instead of capacitor fill up like DRAM DRAM(Dynamic Ram) drawbacks 1 transistor and 1 capacitor Low cost per bit Higher memory density of SRAM High Power consumption because of refresh circuit Heat problems HMC –In Development Intel/Micron originally researched Micron/Samsung/IBM created consortium Uses TSV (Through Silicon Via) to stack memory vertically. Low power consumption Small Size Specs to be released in 2012 Some Specs 15X bandwidth of DDR3 70% reduction in energy per bit than DDR3 Reduced latency with lower queue delays, and increased number of banks. System Architecture makes it extremely efficient on space. Design Actual Picture DRAM 512 MB Memory Stick 512 MB Memory Cube 1 TB/s HMC DRAM Prototype Bandwidth Performance Power Performance The Future Intel speculates super computer by 2018 that can operate at exaflop performance (1018) Will probably be seen first in graphics for memory performance improvement Adaptable to many types of systems because of logic layer Potential for first universal memory (Personal/home computing, Commercial use) Questions, Comments, etc… Thank you.