Design and VHDL Implementation of an Application-Specific Instruction Set Processor Lauri Isola School of Electrical Engineering Thesis submitted for examination for the degree of Master of Science in Technology. Espoo 19.12.2019 Supervisor Prof. Jussi Ryynänen Advisor D.Sc. (Tech.) Marko Kosunen Copyright © 2019 Lauri Isola Aalto University, P.O. BOX 11000, 00076 AALTO www.aalto.fi Abstract of the master’s thesis Author Lauri Isola Title Design and VHDL Implementation of an Application-Specific Instruction Set Processor Degree programme Computer, Communication and Information Sciences Major Signal, Speech and Language Processing Code of major ELEC3031 Supervisor Prof. Jussi Ryynänen Advisor D.Sc. (Tech.) Marko Kosunen Date 19.12.2019 Number of pages 66+45 Language English Abstract Open source processors are becoming more popular. They are a cost-effective option in hardware designs, because using the processor does not require an expensive license. However, a limited number of open source processors are still available. This is especially true for Application-Specific Instruction Set Processors (ASIPs). In this work, an ASIP processor was designed and implemented in VHDL hardware description language. The design was based on goals that make the processor easily customizable, and to have a low resource consumption in a System- on-Chip (SoC) design. Finally, the processor was implemented on an FPGA circuit, where it was tested with a specially designed VGA graphics controller. Necessary software tools, such as an assembler were also implemented for the processor. The assembler was used to write comprehensive test programs for testing and verifying the functionality of the processor. This work also examined some future upgrades of the designed processor. The upgrades include improvements to hardware, software tools and usability. The source codes for the processor, graphics controller and test programs are published under the MIT license, and are available at: http://www.iki.fi/lauri.isola/asip38. Keywords ASIP, CPU, RTL, HDL, FPGA, SoC, programmable logic, embedded systems Aalto-yliopisto, PL 11000, 00076 AALTO www.aalto.fi Diplomityön tiivistelmä Tekijä Lauri Isola Työn nimi Sovelluskohtaisen käskykantaprosessorin suunnittelu ja toteutus VHDL:llä Koulutusohjelma Computer, Communication and Information Sciences Pääaine Signal, Speech and Language Processing Pääaineen koodi ELEC3031 Työn valvoja Prof. Jussi Ryynänen Työn ohjaaja TkT Marko Kosunen Päivämäärä 19.12.2019 Sivumäärä 66+45 Kieli Englanti Tiivistelmä Avoimen lähdekoodin prosessorit ovat yleistymässä. Ne ovat laitteistosuunnitte- lun kannalta kustannustehokas vaihtoehto, koska prosessorin käyttäminen ei vaadi kallista lisenssiä. Avoimen lähdekoodin prosessoreita on tarjolla kuitenkin vielä var- sin rajallinen määrä. Tämä koskee etenkin sovelluskohtaisia käskykantaprosessoreita (ASIP). Tässä työssä on suunniteltu sovelluskohtainen käskykantaprosessori ja toteutet- tu se VHDL-laitteistokuvauskielellä. Suunnittelun lähtökohtina olivat prosessorin vaivaton muokattavuus sekä toteuttaminen järjestelmäpiirille (SoC) mahdollisim- man vähillä resursseilla. Prosessori on toteutettu FPGA-piirille, jossa sitä testattiin erikseen suunnitellulla VGA-grafiikkaohjaimella. Prosessoria varten toteutettiin myös tarvittavat ohjelmistotyökalut, kuten as- sembler-kääntäjä. Sen avulla kirjoitettiin kattavat testiohjelmat, joita käytettiin prosessorin toiminnan testaamiseksi ja todentamiseksi. Tässä työssä tutustuttiin myös prosessorin jatkokehittämiseen. Tarkastelussa olivat laitteistoon, ohjelmistotyökaluihin ja käytettävyyteen liittyvät kehitysideat. Prosessorin, grafiikkaohjaimen sekä testiohjelmien lähdekoodit on julkaistu MIT- lisenssillä ja ne ovat saatavilla osoitteessa: http://www.iki.fi/lauri.isola/asip38. Avainsanat ASIP, CPU, RTL, HDL, FPGA, SoC, ohjelmoitavat piirit, sulautetut järjestelmät 5 Preface I have done a number of electronics projects using a variety of microcontrollers. Although microcontrollers have generally served their job well, they have sometimes lacked features that would have been useful in those projects. The idea of making my own ASIP processor started to seriously interest me when small FPGAs became more affordable to be used in enthusiast-level projects. When using anASIP, the instruction set of the processor, as well as other features, can be specifically designed according to the project. This brings the projects to a whole new level. This thesis is a documentation of the results of my ASIP project. I would like to thank Aalto University especially for Computer Architecture and Digital Microelectronics I & II courses, which contained the basic knowledge of the topic. Thanks also to Nokia Networks for the interest in my ASIP processor. Finally, I would like to thank my family for supporting me during my studies. Espoo, 31.8.2019 Lauri Isola 6 Contents Abstract3 Abstract (in Finnish)4 Preface5 Contents6 Abbreviations9 1 Introduction 10 1.1 Thesis goals............................... 10 1.2 Thesis organization........................... 11 2 Embedded processor technology 12 2.1 Single-purpose processors........................ 12 2.2 General-purpose processors....................... 12 2.3 Application-specific processors..................... 14 3 Processor design 15 3.1 Design objectives............................ 15 3.2 Memory architecture.......................... 15 3.3 Datapath design............................. 16 3.3.1 Program counter........................ 16 3.3.2 Program stack.......................... 16 3.3.3 Registers............................. 17 3.3.4 Data bus............................. 18 3.3.5 Arithmetic logic unit...................... 18 3.3.6 Datapath organization..................... 20 3.4 Instruction set architecture....................... 21 3.4.1 Overview............................ 21 3.4.2 Instruction word........................ 22 3.4.3 Memory operations....................... 23 3.4.4 Accumulator operations.................... 24 3.4.5 Input/Output operations.................... 24 3.4.6 Control operations....................... 25 3.5 Instruction cycle............................ 27 3.5.1 Single-cycle approach...................... 27 3.5.2 Multi-cycle approach...................... 27 3.5.3 Pipelined approach....................... 29 7 3.6 Control unit............................... 29 3.6.1 Structure............................ 29 3.6.2 Control signals......................... 30 3.6.3 PC control............................ 32 4 VHDL implementation 33 4.1 FPGA design flow............................ 33 4.2 Artix-7 FPGA resources........................ 35 4.3 Top level system............................ 36 4.4 Required VHDL packages....................... 37 4.5 ASIP38................................. 37 4.5.1 Block RAM........................... 37 4.5.2 Program counter........................ 38 4.5.3 Program stack.......................... 38 4.5.4 ALU............................... 39 4.5.5 Instruction decode and control................. 39 4.6 Graphics controller........................... 40 4.7 Inputs.................................. 43 4.8 Top level entity............................. 44 4.9 Behavioral simulation.......................... 44 4.10 Synthesis................................. 45 4.11 Implementation............................. 46 5 Verification and testing 48 5.1 Hardware verification.......................... 48 5.2 Assembler................................ 48 5.3 Test programs.............................. 50 5.4 Board-level testing........................... 54 6 Analysis of results 55 6.1 Results of the design process...................... 55 6.2 Processor comparison.......................... 55 7 Future upgrades 58 7.1 Additional hardware.......................... 58 7.2 Software tools.............................. 59 7.3 Bus protocols.............................. 59 8 Conclusion 61 References 63 8 A Source codes 67 A.1 asip38.vhd................................ 67 A.2 display_control.vhd........................... 78 A.3 vga_sync.vhd.............................. 84 A.4 rgb_gen.vhd............................... 86 A.5 line_draw.vhd.............................. 91 A.6 ellipse_draw.vhd............................ 94 A.7 area_paint.vhd............................. 97 A.8 input.vhd................................ 101 A.9 top.vhd................................. 103 A.10 assembler.py............................... 107 9 Abbreviations 3D Three-dimensional AC Accumulator ALU Arithmetic Logic Unit ASIC Application-Specific Integrated Circuit ASIP Application-Specific Instruction Set Processor BRAM Block RAM CISC Complex Instruction Set Computer CPI Cycles Per Instruction CPU Central Processing Unit DSP Digital Signal Processing FF Flip-Flop FPGA Field-Programmable Gate Array FSM Finite State Machine HDL Hardware Description Language HLL High-Level Language I/O Input/Output IC Integrated Circuit IR Instruction Register ISA Instruction Set Architecture ISR Interrupt Service Routine IP Intellectual Property LUT Look-up Table NRE Non-Recurring Engineering PC Program Counter PLD Programmable Logic Device RAM Random Access Memory ROM Read-Only Memory RISC Reduced Instruction Set Computer RTL Register Transfer Level RTOS Real-Time Operating System SoC System-on-Chip SP Stack Pointer TOS Top Of Stack uC Microcontroller uP Microprocessor VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit VGA Video Graphics Array WNS Worst Negative Slack 10 1 Introduction A soft processor