VAX 7000/10000 KA7AA CPU Technical Manual Order Number EK—KA7AA—TM.001 The KA7AA is a VAX CPU module designed for the LSB platform. It is based on the NVAX+ microprocessor and is used in the VAX 7000 and VAX 10000 computer systems. It supports up to seven MS7AA memory modules in a uniprocessor configuration and one IOP module per system. Used in a single-processor system, the KA7AA module achieves a minimum scalar performance equivalent to that of more than 20 VAX 11/780 systems. A multiprocessor system supports up to six KA7AA CPU modules. First Printing, December 1992 The information in this document is subject to change without notice and should not be construed as a com- mitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of soft- ware or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. Copyright © 1992 by Digital Equipment Corporation. All Rights Reserved. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation: Alpha AXP DECUS VAXBI AXP DWMVA VAXELN DEC OpenVMS VMScluster DECchip ULTRIX XMI DEC LANcontroller UNIBUS The AXP logo DECnet VAX d OSF/1 is a registered trademark of the Open Software Foundation, Inc. FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio frequency en- ergy. The equipment has been type tested and found to comply with the limits for a Class A computing de- vice pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio frequency interference when operated in a commercial environment. Operation of this equipment in a residential area may cause interference, in which case the user at his own expense may be required to take measures to correct the interference. Contents Preface ............................................................................................................................................. xi Chapter 1 CPU Module Overview 1.1 NVAX+ CPU Chip ......................................................................................................... 1-3 1.2 Backup Cache (B-Cache) .............................................................................................. 1-4 1.3 LSB Interface (LEVI) ................................................................................................... 1-4 Chapter 2 CPU Chip 2.1 Data Types..................................................................................................................... 2-2 2.2 Instruction Set .............................................................................................................. 2-2 2.3 ........................................................................................................................................ 2-2 2.4 Address Space ............................................................................................................... 2-3 2.4.1 Virtual Address Space ............................................................................................ 2-3 2.4.2 Physical Address Space .......................................................................................... 2-3 2.5 Memory Management ................................................................................................... 2-4 2.5.1 System Space Address Translation ....................................................................... 2-4 2.5.2 Process Space Address Translation ....................................................................... 2-5 2.5.2.1 P0 Region Address Translation ....................................................................... 2-5 2.5.2.2 P1 Region Address Translation ....................................................................... 2-5 2.5.3 Page Table Entry Format....................................................................................... 2-6 2.5.4 Translation Buffer .................................................................................................. 2-7 2.5.5 Memory Management Control ............................................................................... 2-7 2.6 Exceptions and Interrupts ............................................................................................ 2-9 2.6.1 Exceptions ............................................................................................................. 2-10 2.6.1.1 Arithmetic Exceptions ................................................................................... 2-11 2.6.1.2 Memory Management Exceptions ................................................................. 2-12 2.6.1.3 Emulated Instruction Exceptions ................................................................. 2-13 2.6.1.4 System Failure Exceptions ............................................................................ 2-14 2.6.2 Interrupts .............................................................................................................. 2-15 2.6.2.1 External Interrupt Requests ........................................................................ 2-16 2.6.2.2 Internal Interrupt Requests .......................................................................... 2-16 2.7 System Control Block.................................................................................................. 2-18 2.8 Process Structure ........................................................................................................ 2-22 2.9 Functional Partitions .................................................................................................. 2-25 2.9.1 Ibox ........................................................................................................................ 2-26 2.9.2 Ebox and Microsequencer .................................................................................... 2-27 2.9.3 Fbox ....................................................................................................................... 2-28 2.9.4 Mbox ...................................................................................................................... 2-28 2.9.5 Cbox ....................................................................................................................... 2-29 2.10 General Purpose Registers ......................................................................................... 2-30 iii 2.11 Internal Processor Registers ...................................................................................... 2-31 2.11.1 Identification Registers ........................................................................................ 2-35 CPUID—CPU Identification Register ................................................................. 2-36 SID—System Identification Register .................................................................. 2-37 2.11.2 Ibox Registers ....................................................................................................... 2-38 VMAR—VIC Memory Address Register.............................................................. 2-39 VTAG—VIC Tag Register .................................................................................... 2-40 VDATA—VIC Data Register ................................................................................ 2-41 ICSR—Ibox Control and Status Register ............................................................ 2-42 BPCR—Branch Prediction Control Register...................................................... 2-43 2.11.3 Ebox Registers ...................................................................................................... 2-45 PCSCR—Patchable Control Store Control Register ........................................... 2-46 ECR—Ebox Control Register ............................................................................... 2-48 2.11.4 Mbox Registers ..................................................................................................... 2-50 MP0BR—Mbox P0 Base Register ........................................................................ 2-51 MP0LR—Mbox P0 Length Register .................................................................... 2-52 MP1BR—Mbox P1 Base Register ........................................................................ 2-53 MP1LR—Mbox P1 Length Register .................................................................... 2-54 MSBR—Mbox System Base Register .................................................................. 2-55 MSLR—Mbox System Length Register............................................................... 2-56 MMAPEN—Mbox Map Enable Register ............................................................. 2-57 PAMODE—Physical Address Mode Register ..................................................... 2-58 MMEADR—MME Address Register ................................................................... 2-59 MMEPTE—MME PTE Address Register............................................................ 2-60 MMESTS—MME Status Register ....................................................................... 2-61 TBADR—Translation Buffer Parity Address Register....................................... 2-63 TBSTS—Translation Buffer Parity Status Register .......................................... 2-64 PCADR—P-Cache Parity