Chrontel CH7022 CH7022 SDTV/EDTV/HDTV Encoder Features General Description • SDVO [1] to SDTV/EDTV/HDTV conversion The CH7022 is a Display Controller device which accepts a supporting up to 160 MHz pixel clock digital graphics high speed AC coupled serial differential • SDVO to VGA conversion supporting up to RGB input signal, and encodes and transmits data through 1600x1200 resolution [2] analog SDTV ports (analog composite, s-video, VGA or • EDTV/HDTV support for 480p, 576p, 720p, 1080i YPrPb) or an analog EDTV/HDTV port (YPrPb). The device and 1080p is able to encode the video signals and generate • Support for NTSC, PAL and SECAM color synchronization signals for NTSC, PAL and SECAM SDTV modulation. standards, as well as analog EDTV and HDTV interface • CGMS-A support for SDTV, EDTV and HDTV standards and graphics standards up to UXGA. The device • High-speed SDVO (1G~2Gbps) AC-coupled serial accepts one channel of RGB data over three pairs of serial differential RGB inputs data ports. • Flexible true scale rendering engine supports The TV-Out processor will perform scaling to convert VGA overscan compensation in all SDTV/EDTV and [3] frames to all the supported TV output standards. Adaptive de- HDTV output resolutions flicker filter provides superior text display. Large numbers of • Text enhancement filter in scan conversion input graphics resolutions are supported up to 160 MHz pixel • Adaptive de-flicker filter with up to 7 lines of rate with full vertical and horizontal overscan compensation in filtering in scan conversion all output standards. A high accuracy low jitter phase locked • Contrast/Brightness/Sharpness control for TV output. loop is integrated to create outstanding video quality. • Hue/Saturation Control for TV output. • Support for SCART connector In addition to scaling modes, bypass modes are included • Support for EDTV / HDTV D-Connector which perform color space conversion to all the TV standards • Outputs CVBS, S-Video, VGA and YPbPr and generate and insert all the TV sync signals, or output • Support for VGA bypass VGA style analog RGB. • TV / Monitor connection detect • Programmable power management Different analog video connectors are supported including • Four 10-bit video DAC outputs composite, s-video, YPrPb, SCART, D-connector and VGA • Three sets of DAC outputs supporting SDTV / connector. EDTV / HDTV / VGA connectors • Fully programmable through serial port CGMS-A is also provided up to 1080i resolution. • [1] Configuration through Intel® SDVO OpCode TM • Complete Windows driver support CH7022 is a chip without Macrovision encoding. • Offered in 64-pin LQFP and 64-pin QFN package [1] Intel Proprietary. [2] For the modes higher than 160 MHz pixel rate, please contact Chrontel Application Department for detail. [3] Patent pending 201-0000-099 Rev. 3.2, 1/07/2014 1 CHRONTEL CH7022 Serial AS XI/FIN,XO SPC 2 PLL Port TVCLK(+,-) Control SPD RESET* BCO/VSYNC C/HSYNC Control SC_DDC D1,D2,D3 SD_DDC 3 SC_PROM SD_PROM CVBS, S-Video, NTSC/PAL/ Clock Color Space RGB, YPbPr SDVO_Clk(+,-) SECAM 2 Driver Conversion Encoder DAC 3 Scaling DACA[3:0] Scan Conv Flicker Filt DAC 2 Video DACB[2:0] 10bit-8bit Switch MUX decoder DAC 1 HDTV YPbPr Encoder DACC[2:0] DAC 0 SDVO_R(+,-) Data Latch, RGB, Bypass SDVO_G(+,-) Four 6 Serial to Parallel SDVO_B(+,-) 10-bit DAC's ISET Figure 1: Functional Block Diagram 2 201-0000-099 Rev. 3.2, 1/07/2014 CHRONTEL CH7022 Table of Contents 1.0 Pin-Out ____________________________________________________________________ 5 1.1 Package Diagram ___________________________________________________________________5 1.2 Pin Description _____________________________________________________________________7 2.0 Functional Description_______________________________________________________ 10 2.1 Input Interface_____________________________________________________________________10 2.2 TV Output Operation _______________________________________________________________10 2.3 VGA Bypass Operation _____________________________________________________________13 2.4 Command Interface ________________________________________________________________13 2.5 D-Connector ______________________________________________________________________14 2.6 Boundary scan Test_________________________________________________________________14 3.0 Register Control ____________________________________________________________ 16 4.0 Electrical Specifications ______________________________________________________ 17 4.1 Absolute Maximum Ratings __________________________________________________________17 4.2 Recommended Operating Conditions___________________________________________________17 4.3 Electrical Characteristics ____________________________________________________________18 4.4 DC Specifications __________________________________________________________________19 4.5 AC Specifications __________________________________________________________________21 5.0 Package Dimensions _________________________________________________________ 23 6.0 Revision History ____________________________________________________________ 25 201-0000-099 Rev. 3.2, 1/07/2014 3 CHRONTEL CH7022 Figures and Tables List of Figures Figure 1: Functional Block Diagram .............................................................................................................................2 Figure 2: 64-Pin LQFP Package....................................................................................................................................5 Figure 3: 64-Pin QFN Package......................................................................................................................................6 Figure 4: Control Bus Switch ......................................................................................................................................13 Figure 5: NAND Tree Connection ..............................................................................................................................14 Figure 6: 64 Pin LQFP (Exposed Pad) Package ..........................................................................................................23 Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm) .........................................................................................................24 List of Tables Table 1: Pin Description................................................................................................................................................7 Table 2: CH7022 supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns....................................10 Table 3: Various VGA resolutions. .............................................................................................................................11 Table 4: Supported SDTV standards ...........................................................................................................................11 Table 5: Supported EDTV/HDTV standards...............................................................................................................12 Table 6: Video DAC Configurations for CH7022.......................................................................................................12 Table 7: Video Format Identification Using DL1, DL2 and DL3 ...............................................................................14 Table 8: Signal Order in the NAND Tree Testing.......................................................................................................15 Table 9: Signals not Tested in NAND Test besides power pins..................................................................................15 Table 10: Revisions .....................................................................................................................................................25 4 201-0000-099 Rev. 3.2, 1/07/2014 CHRONTEL CH7022 1.0 Pin-Out 1.1 Package Diagram 1.1.1 The 64-Pin LQFP Package Diagram T2 RPLL AGND AVDD AGND AVDD AGND AVDD SDVO_B- SDVO_B+ SDVO_G- SDVO_G+ SDVO_R- SDVO_R+ SDVO_CLK- SDVO_CLK+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 T1 1 48 DL3 SD_DDC 2 47 DL2 SC_DDC 3 46 DL1 SD_PROM 4 45 AGND_TVPLL2 SC_PROM 5 44 TVCLK- DVDD 6 43 TVCLK+ RESET* 7 Chrontel 42 AVDD_TVPLL2 AS 8 41 AVDD_TVPLL1 DGND 9 CH7022 40 XO DGND 10 39 XI/FIN SPD 11 38 AGND_TVPLL1 SPC 12 37 DGND DVDD 13 36 VSYNC BSCAN 14 35 DVDD T3 15 34 CHSYNC VDAC2 16 33 V5V 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 17 ISET GDAC1 GDAC2 VDAC1 VDAC0 GDAC0 DACA[3] DACA[2] DACB[2] DACC[2] DACA[1] DACB[1] DACC[1] DACA[0] DACB[0] DACC[0] Figure 2: 64-Pin LQFP Package 201-0000-099 Rev. 3.2, 1/07/2014 5 CHRONTEL CH7022 1.1.2 The 64-Pin QFN Package Diagram T2 AVDD AGND AVDD AGND AVDD RPLL AGND SDVO_B- SDVO_B+ SDVO_G- SDVO_G+ SDVO_R- SDVO_R+ SDVO_CLK- SDVO_CLK+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 T1 1 48 DL3 SD_DDC 2 47 DL2 SC_DDC 3 46 DL1 SD_PROM 4 45 AGND_TVPLL2 SC_PROM 5 44 TVCLK- DVDD 6 43 TVCLK+ RESET* 7 Chrontel 42 AVDD_TVPLL2 AS 8 41 AVDD_TVPLL1 DGND 9 CH7022 40 XO DGND 10 39 XI/FIN SPD 11 38 AGND_TVPLL1 SPC 12 37 DGND DVDD 13 36 VSYNC BSCAN 14 35 DVDD T3 15 34 CHSYNC VDAC2 16 33 V5V 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ISET GDAC0 GDAC2 VDAC1 GDAC1 VDAC0 DACA[3] DACA[2] DACB[2] DACC[2] DACA[1] DACB[1] DACC[1] DACA[0] DACB[0] DACC[0] Figure 3: 64-Pin QFN Package 6 201-0000-099 Rev. 3.2, 1/07/2014 CHRONTEL CH7022 1.2 Pin Description Table 1: Pin Description Pin # Type Symbol Description 1,51 Out T1, T2 Test These pins are reserved for factory test and default to high impedance.