European Commission IST programme Future and Emerging Technologies Technology Roadmap for Nanoelectronics Second Edition, November 2000 Editor: R. Compañó Technology Roadmap for Nanoelectronics Foreword The IT revolution is based on an “exponential” rate of technological progress. For example, internet traffic doubles every 6 months, wireless capacity doubles every 9, optical capacity doubles every 12, magnetic information storage doubles every 15, etc. The most famous example is “Moore’s law” which indicates that the performance of semiconductor devices doubles every 18 months. Moore’s observation has been valid for three decades and has been a fundamental tool for business planning in the semiconductor industry. Fundamental laws of physics limit the shrinkage of CMOS on which Moore’s Law is based, at least on current approaches. Even before these physical limits are reached there are strong indications that severe engineering pro- blems, as well as the need for huge investment, may slow down the growth in inte- grated circuit performance. The continuation of the IT revolution is predicated on new ideas for information storage or processing, leading to future applications. One option is to look for mechanisms that operate at the nanoscale and exploit quantum effects. The objective of this document is to monitor device concepts currently under investigation, to discuss the feasibility of their large scale integration and of ways to fabricate them. Giving a description of the state of the art in a field is an exercise which is commonly undertaken with success; extrapolating into the future is not so obvious. Making predictions in an emergent field is even more difficult. By its nature, no forecast can reflect all the views of all the experts in the field; it can try, at best, to reflect a con- sensus of most of their views. In order to arrive at a “common view”, the editor has collected information from many sources. In particular, he has relied greatly upon the discussions of the six monthly MELARI/NID workshops whose participants are drawn from more than sixty distinct Europe research groups working in different areas of nanoelectronics. The first technology roadmap for nanoelectronics was published by L. Molenkamp, D. Paul and R. Compañó in April 1999 and this new edition follows the same for- mat. This new edition has been expanded by new chapters reflecting new tendencies. In particular, P. Lindelof and L. Samuelson have provided the information for Chapter 3.6 on wave interference devices, C. Sotomayor for Chapter 4.2.3 on prin- ting techniques, Ch. Pacha and W. Prost for Chapter 3.2.1 on interband tunnelling devices and M. Macucci for Chapter 3.4.3 on molecular approaches. In addition, many persons have contributed by updating the chapters on Emerging Devices, on Nanofabrication and Circuits & Architectures and the tables on the performance forecast. They are mentioned in the back of this document. R. Compañó has been in charge of balancing the different views and summarising the conclusions. Many top nanotechnology experts contributed to this document, but predictions can never be guaranteed. This roadmap should be understood as a document that mo- nitors progress and discusses tendencies in the hope that it may help the reader to appreciate strengths, weaknesses, threats and opportunities of different technologies. Although breakthroughs are not usually predicted, they very often occur as unex- pected results when working towards predicted targets. Simon Bensasson Head of Unit “Future and Emerging Technologies” 2 Technology Roadmap for Nanoelectronics CONTENTS 1. Introduction . .7 1.1. Markets . .7 1.2. Applications . .9 1.3. Public Investments in Nanotechnologies . .14 2. Reference Point: MOSFETS . .18 2.1. Theoretical Limits . .18 2.2. Technology Limits . .19 2.3. Economical Limits . .19 2.4. Major Challenges and Difficulties . .20 3. Emerging Devices . .21 3.1. Single Electron Tunnelling Devices . .21 3.1.1. Single Electron Transistors . .21 3.1.2. Nano-flash Device . .22 3.1.3. Yano Memory . .23 3.1.4. Device Parameters and Future Challenges . .23 3.2. Tunnelling Diodes . .25 3.2.1. Interband Tunelling Diode (ITD) . .25 3.2.2. Resonant Tunnelling Diode . .26 3.2.3. Tunnel Diodes Performance . .27 3.2.4. Concepts for Three Terminal Resonant Tunnelling Devices . .28 3.2.5. Major Challenges and Difficulties for TDs . .30 3.3. Rapid Single Flux Quantum Logic . .31 3.3.1. Principle of Operation . .31 3.3.2. Technology, Critical Dimensions and Performance . .31 3.3.3. Major Challenges and Difficulties for RSFQ . .32 3.4. Molecular Nanoelectronics . .33 3.4.1. Electric-field Based Molecular Switching Devices . .33 3.4.2. Alternative Molecular Components . .34 3.4.3. Molecular Modelling . .35 3.4.4. Major Challenges and Difficulties for Molecular Electronics . .37 3.5. Spin Devices . .38 3.5.1. Spin Valve Devices . .38 3.5.2. Tunnel Junction Devices . .39 3.5.3 Spin Injection Devices . .39 3.5.4. Performance . .40 3.5.5. Challenges and Difficulties . .40 3.6. Wave Interference Devices: Electronic Waveguiding and Quantum Interference Devices . .42 3.6.1. The Basics of Coherent Switching and Interference . .42 3.6.2. Technology and Critical Dimensions . .43 3.6.3. Quantum Point Contacts and Electronic Waveguides . .43 3.6.4. Double Electron Waveguide Devices . .43 3.6.5. The 3-terminal (Y-Branch) Switching Devices . .44 3.6.6. Major Challenges and Difficulties for Electron Interference and Switching Devices . .45 3 Technology Roadmap for Nanoelectronics 4. Nanofabrication . .46 4.1. Lithography for CMOS Technology . .48 4.1.1. Optical Lithography . .48 4.1.2. Extreme Ultraviolet Lithography . .48 4.1.3. X-ray Proximity Lithography . .48 4.1.4. E-beam Projection Lithography and Scalpel . .49 4.1.5. Ion Beam Projection . .50 4.2. Emerging Nanofabrication Methods . .51 4.2.1. Electron Beam Nanolithography . .51 4.2.2. Scanning Probe Methods . .52 4.2.3. Printing . .52 4.2.4. Bottom Up Approaches . .57 4.3. Comparison of Fabrication Techniques . .58 5. Circuits and Systems . .60 5.1. Design Strategies: Interconnect Problems and Design Complexity . .60 5.1.1. Impact of Increasing Clocking Frequencies on Nanoscale Circuits . .62 5.1.2. Local Architectures . .62 5.2. Novel Circuitry . .63 5.2.1. Resonant Tunnelling Device Circuits . .63 5.2.2. QCA circuits . .65 5.3. Current Trends in Novel System Architectures . .68 5.3.1. Starting Point: Systems on Chip and Innovations in Microprocessor Designs . ..